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18f3c78092
instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157234 91177308-0d34-0410-b5e6-96231b3b80d8
146 lines
4.6 KiB
C++
146 lines
4.6 KiB
C++
//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSSUBTARGET_H
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#define MIPSSUBTARGET_H
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "MipsGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class MipsSubtarget : public MipsGenSubtargetInfo {
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virtual void anchor();
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public:
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// NOTE: O64 will not be supported.
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enum MipsABIEnum {
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UnknownABI, O32, N32, N64, EABI
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};
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protected:
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enum MipsArchEnum {
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Mips32, Mips32r2, Mips64, Mips64r2
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};
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// Mips architecture version
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MipsArchEnum MipsArchVersion;
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// Mips supported ABIs
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MipsABIEnum MipsABI;
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// IsLittle - The target is Little Endian
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bool IsLittle;
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// IsSingleFloat - The target only supports single precision float
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// point operations. This enable the target to use all 32 32-bit
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// floating point registers instead of only using even ones.
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bool IsSingleFloat;
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// IsFP64bit - The target processor has 64-bit floating point registers.
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bool IsFP64bit;
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// IsFP64bit - General-purpose registers are 64 bits wide
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bool IsGP64bit;
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// HasVFPU - Processor has a vector floating point unit.
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bool HasVFPU;
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// isLinux - Target system is Linux. Is false we consider ELFOS for now.
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bool IsLinux;
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/// Features related to the presence of specific instructions.
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// HasSEInReg - SEB and SEH (signext in register) instructions.
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bool HasSEInReg;
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// HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
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bool HasCondMov;
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// HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
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// instructions.
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bool HasMulDivAdd;
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// HasMinMax - MIN and MAX instructions.
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bool HasMinMax;
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// HasSwap - Byte and half swap instructions.
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bool HasSwap;
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// HasBitCount - Count leading '1' and '0' bits.
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bool HasBitCount;
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// InMips16 -- can process Mips16 instructions
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bool InMips16Mode;
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InstrItineraryData InstrItins;
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public:
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virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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AntiDepBreakMode& Mode,
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RegClassVector& CriticalPathRCs) const;
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/// Only O32 and EABI supported right now.
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bool isABI_EABI() const { return MipsABI == EABI; }
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bool isABI_N64() const { return MipsABI == N64; }
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bool isABI_N32() const { return MipsABI == N32; }
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bool isABI_O32() const { return MipsABI == O32; }
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unsigned getTargetABI() const { return MipsABI; }
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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MipsSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool little);
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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bool hasMips32() const { return MipsArchVersion >= Mips32; }
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bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
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MipsArchVersion == Mips64r2; }
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bool hasMips64() const { return MipsArchVersion >= Mips64; }
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bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
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bool hasMips32r2Or64() const { return hasMips32r2() || hasMips64(); }
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bool isLittle() const { return IsLittle; }
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bool isFP64bit() const { return IsFP64bit; }
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bool isGP64bit() const { return IsGP64bit; }
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bool isGP32bit() const { return !IsGP64bit; }
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bool isSingleFloat() const { return IsSingleFloat; }
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bool isNotSingleFloat() const { return !IsSingleFloat; }
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bool hasVFPU() const { return HasVFPU; }
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bool inMips16Mode() const { return InMips16Mode; }
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bool isLinux() const { return IsLinux; }
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bool hasStandardEncoding() const { return !inMips16Mode(); }
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/// Features related to the presence of specific instructions.
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bool hasSEInReg() const { return HasSEInReg; }
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bool hasCondMov() const { return HasCondMov; }
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bool hasMulDivAdd() const { return HasMulDivAdd; }
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bool hasMinMax() const { return HasMinMax; }
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bool hasSwap() const { return HasSwap; }
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bool hasBitCount() const { return HasBitCount; }
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};
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} // End llvm namespace
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#endif
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