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These recently all grew a unique_ptr<TargetLoweringObjectFile> member in r221878. When anyone calls a virtual method of a class, clang-cl requires all virtual methods to be semantically valid. This includes the implicit virtual destructor, which triggers instantiation of the unique_ptr destructor, which fails because the type being deleted is incomplete. This is just part of the ongoing saga of PR20337, which is affecting Blink as well. Because the MSVC ABI doesn't have key functions, we end up referencing the vtable and implicit destructor on any virtual call through a class. We don't actually end up emitting the dtor, so it'd be good if we could avoid this unneeded type completion work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222480 91177308-0d34-0410-b5e6-96231b3b80d8
220 lines
7.5 KiB
C++
220 lines
7.5 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "X86TargetObjectFile.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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extern "C" void LLVMInitializeX86Target() {
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// Register the target.
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RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
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RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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if (TT.isOSBinFormatMachO()) {
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if (TT.getArch() == Triple::x86_64)
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return make_unique<X86_64MachoTargetObjectFile>();
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return make_unique<TargetLoweringObjectFileMachO>();
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}
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if (TT.isOSLinux())
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return make_unique<X86LinuxTargetObjectFile>();
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if (TT.isOSBinFormatELF())
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return make_unique<TargetLoweringObjectFileELF>();
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if (TT.isKnownWindowsMSVCEnvironment())
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return make_unique<X86WindowsTargetObjectFile>();
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if (TT.isOSBinFormatCOFF())
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return make_unique<TargetLoweringObjectFileCOFF>();
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llvm_unreachable("unknown subtarget type");
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}
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/// X86TargetMachine ctor - Create an X86 target.
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///
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X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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TLOF(createTLOF(Triple(getTargetTriple()))),
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Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
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// default to hard float ABI
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if (Options.FloatABIType == FloatABI::Default)
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this->Options.FloatABIType = FloatABI::Hard;
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// Windows stack unwinder gets confused when execution flow "falls through"
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// after a call to 'noreturn' function.
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// To prevent that, we emit a trap for 'unreachable' IR instructions.
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// (which on X86, happens to be the 'ud2' instruction)
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if (Subtarget.isTargetWin64())
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this->Options.TrapUnreachable = true;
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initAsmInfo();
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}
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X86TargetMachine::~X86TargetMachine() {}
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const X86Subtarget *
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X86TargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeSet FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function before we can generate a subtarget. We also need to use
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// it as a key for the subtarget since that can be the only difference
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// between two functions.
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Attribute SFAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
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bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)
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? SFAttr.getValueAsString() == "true"
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: Options.UseSoftFloat;
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auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"
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: "use-soft-float=false")];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
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Options.StackAlignmentOverride);
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}
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return I.get();
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}
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//===----------------------------------------------------------------------===//
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// Command line options for x86
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//===----------------------------------------------------------------------===//
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static cl::opt<bool>
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UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
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cl::desc("Minimize AVX to SSE transition penalty"),
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cl::init(true));
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//===----------------------------------------------------------------------===//
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// X86 Analysis Pass Setup
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//===----------------------------------------------------------------------===//
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void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
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// Add first the target-independent BasicTTI pass, then our X86 pass. This
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// allows the X86 pass to delegate to the target independent layer when
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// appropriate.
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PM.add(createBasicTargetTransformInfoPass(this));
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PM.add(createX86TargetTransformInfoPass(this));
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86 Code Generator Pass Configuration Options.
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class X86PassConfig : public TargetPassConfig {
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public:
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X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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X86TargetMachine &getX86TargetMachine() const {
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return getTM<X86TargetMachine>();
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}
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const X86Subtarget &getX86Subtarget() const {
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return *getX86TargetMachine().getSubtargetImpl();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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bool addILPOpts() override;
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bool addPreRegAlloc() override;
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bool addPostRegAlloc() override;
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bool addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new X86PassConfig(this, PM);
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}
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void X86PassConfig::addIRPasses() {
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addPass(createAtomicExpandPass(&getX86TargetMachine()));
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TargetPassConfig::addIRPasses();
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}
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bool X86PassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
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// For ELF, cleanup any local-dynamic TLS accesses.
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if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
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addPass(createCleanupLocalDynamicTLSPass());
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addPass(createX86GlobalBaseRegPass());
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return false;
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}
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bool X86PassConfig::addILPOpts() {
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addPass(&EarlyIfConverterID);
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return true;
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}
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bool X86PassConfig::addPreRegAlloc() {
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return false; // -print-machineinstr shouldn't print after this.
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}
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bool X86PassConfig::addPostRegAlloc() {
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addPass(createX86FloatingPointStackifierPass());
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return true; // -print-machineinstr should print after this.
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}
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bool X86PassConfig::addPreEmitPass() {
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bool ShouldPrint = false;
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if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
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addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
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ShouldPrint = true;
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}
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if (UseVZeroUpper) {
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addPass(createX86IssueVZeroUpperPass());
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ShouldPrint = true;
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}
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createX86PadShortFunctions());
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addPass(createX86FixupLEAs());
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ShouldPrint = true;
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}
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return ShouldPrint;
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}
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