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When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
687 lines
27 KiB
C++
687 lines
27 KiB
C++
//===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the Emit routines for the ScheduleDAG class, which creates
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// MachineInstrs according to the computed schedule.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-RA-sched"
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#include "ScheduleDAGSDNodes.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void ScheduleDAGSDNodes::
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EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
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unsigned VRBase = 0;
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if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
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// Just use the input register directly!
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SDValue Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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return;
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}
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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bool MatchReg = true;
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const TargetRegisterClass *UseRC = NULL;
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if (!IsClone && !IsCloned)
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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bool Match = true;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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Match = false;
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} else if (DestReg != SrcReg)
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Match = false;
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} else {
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for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
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SDValue Op = User->getOperand(i);
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if (Op.getNode() != Node || Op.getResNo() != ResNo)
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continue;
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MVT VT = Node->getValueType(Op.getResNo());
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if (VT == MVT::Other || VT == MVT::Flag)
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continue;
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Match = false;
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if (User->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC = 0;
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if (i+II.getNumDefs() < II.getNumOperands())
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RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
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if (!UseRC)
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UseRC = RC;
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else if (RC) {
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if (UseRC->hasSuperClass(RC))
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UseRC = RC;
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else
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assert((UseRC == RC || RC->hasSuperClass(UseRC)) &&
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"Multiple uses expecting different register classes!");
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}
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}
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}
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}
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MatchReg &= Match;
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if (VRBase)
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break;
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}
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MVT VT = Node->getValueType(ResNo);
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const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
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SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
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// Figure out the register class to create for the destreg.
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if (VRBase) {
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DstRC = MRI.getRegClass(VRBase);
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} else if (UseRC) {
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assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
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DstRC = UseRC;
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} else {
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DstRC = TLI->getRegClassFor(VT);
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}
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// If all uses are reading from the src physical register and copying the
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// register is either impossible or very expensive, then don't create a copy.
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if (MatchReg && SrcRC->getCopyCost() < 0) {
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VRBase = SrcReg;
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} else {
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// Create the reg, emit the copy.
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VRBase = MRI.createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
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DstRC, SrcRC);
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assert(Emitted && "Unable to issue a copy instruction!\n");
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(void) Emitted;
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}
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SDValue Op(Node, ResNo);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
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unsigned ResNo) const {
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if (!Node->hasOneUse())
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return 0;
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SDNode *User = *Node->use_begin();
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == ResNo) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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return Reg;
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}
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return 0;
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}
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void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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bool IsClone, bool IsCloned,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
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"IMPLICIT_DEF should have been handled as a special case elsewhere!");
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for (unsigned i = 0; i < II.getNumDefs(); ++i) {
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// If the specific node value is only used by a CopyToReg and the dest reg
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// is a vreg in the same register class, use the CopyToReg'd destination
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// register instead of creating a new vreg.
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unsigned VRBase = 0;
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const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
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if (II.OpInfo[i].isOptionalDef()) {
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// Optional def must be a physical register.
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unsigned NumResults = CountResults(Node);
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VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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if (!VRBase && !IsClone && !IsCloned)
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node &&
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User->getOperand(2).getResNo() == i) {
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unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
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if (RegRC == RC) {
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VRBase = Reg;
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MI->addOperand(MachineOperand::CreateReg(Reg, true));
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break;
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}
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}
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}
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}
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// Create the result registers for this node and add the result regs to
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// the machine instruction.
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if (VRBase == 0) {
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assert(RC && "Isn't a register operand!");
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VRBase = MRI.createVirtualRegister(RC);
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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}
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SDValue Op(Node, i);
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if (IsClone)
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VRBaseMap.erase(Op);
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bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
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isNew = isNew; // Silence compiler warning.
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assert(isNew && "Node emitted out of order - early");
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}
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}
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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if (Op.isMachineOpcode() &&
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Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
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// Add an IMPLICIT_DEF instruction before every use.
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unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
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// IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
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// does not include operand register class info.
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if (!VReg) {
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const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
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VReg = MRI.createVirtualRegister(RC);
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}
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BuildMI(BB, Op.getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF),VReg);
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return VReg;
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}
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DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
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assert(I != VRBaseMap.end() && "Node emitted out of order - late");
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return I->second;
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}
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/// AddRegisterOperand - Add the specified register as an operand to the
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/// specified machine instr. Insert register copies if the register is
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/// not in the required register class.
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void
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ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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// Get/emit the operand.
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unsigned VReg = getVR(Op, VRBaseMap);
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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const TargetInstrDesc &TID = MI->getDesc();
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bool isOptDef = IIOpNum < TID.getNumOperands() &&
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TID.OpInfo[IIOpNum].isOptionalDef();
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// If the instruction requires a register in a different class, create
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// a new virtual register and copy the value into it.
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if (II) {
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const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *DstRC = 0;
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if (IIOpNum < II->getNumOperands())
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DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
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assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
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"Don't have operand info for this instruction!");
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if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
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unsigned NewVReg = MRI.createVirtualRegister(DstRC);
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bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
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DstRC, SrcRC);
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assert(Emitted && "Unable to issue a copy instruction!\n");
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(void) Emitted;
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VReg = NewVReg;
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}
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}
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MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
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}
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap) {
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if (Op.isMachineOpcode()) {
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AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
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} else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
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} else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
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const ConstantFP *CFP = F->getConstantFPValue();
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MI->addOperand(MachineOperand::CreateFPImm(CFP));
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} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
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} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
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TGA->getTargetFlags()));
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} else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
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} else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
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} else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
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JT->getTargetFlags()));
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
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int Offset = CP->getOffset();
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unsigned Align = CP->getAlignment();
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const Type *Type = CP->getType();
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// MachineConstantPool wants an explicit alignment.
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if (Align == 0) {
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Align = TM.getTargetData()->getPrefTypeAlignment(Type);
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if (Align == 0) {
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// Alignment of vector types. FIXME!
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Align = TM.getTargetData()->getTypeAllocSize(Type);
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}
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}
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unsigned Idx;
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if (CP->isMachineConstantPoolEntry())
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Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
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else
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Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
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MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
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CP->getTargetFlags()));
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} else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
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ES->getTargetFlags()));
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} else {
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assert(Op.getValueType() != MVT::Other &&
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Op.getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
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}
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}
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/// getSuperRegisterRegClass - Returns the register class of a superreg A whose
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/// "SubIdx"'th sub-register class is the specified register class and whose
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/// type matches the specified type.
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static const TargetRegisterClass*
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getSuperRegisterRegClass(const TargetRegisterClass *TRC,
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unsigned SubIdx, MVT VT) {
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// Pick the register class of the superegister for this type
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for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
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E = TRC->superregclasses_end(); I != E; ++I)
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if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
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return *I;
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assert(false && "Couldn't find the register class");
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return 0;
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}
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap){
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unsigned VRBase = 0;
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unsigned Opc = Node->getMachineOpcode();
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// If the node is only used by a CopyToReg and the dest reg is a vreg, use
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// the CopyToReg'd destination register instead of creating a new vreg.
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for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
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UI != E; ++UI) {
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SDNode *User = *UI;
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if (User->getOpcode() == ISD::CopyToReg &&
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User->getOperand(2).getNode() == Node) {
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unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
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VRBase = DestReg;
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break;
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}
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}
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}
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if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
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unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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// Create the extract_subreg machine instruction.
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MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
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TII->get(TargetInstrInfo::EXTRACT_SUBREG));
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// Figure out the register class to create for the destreg.
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unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
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const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
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assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
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// Figure out the register class to create for the destreg.
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// Note that if we're going to directly use an existing register,
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// it must be precisely the required class, and not a subclass
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// thereof.
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if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
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// Create the reg
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assert(SRC && "Couldn't find source register class");
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VRBase = MRI.createVirtualRegister(SRC);
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}
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// Add def, source, and subreg index
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MI->addOperand(MachineOperand::CreateReg(VRBase, true));
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AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
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MI->addOperand(MachineOperand::CreateImm(SubIdx));
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BB->insert(InsertPos, MI);
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} else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
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Opc == TargetInstrInfo::SUBREG_TO_REG) {
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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SDValue N2 = Node->getOperand(2);
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unsigned SubReg = getVR(N1, VRBaseMap);
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unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
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const TargetRegisterClass *TRC = MRI.getRegClass(SubReg);
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const TargetRegisterClass *SRC =
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getSuperRegisterRegClass(TRC, SubIdx,
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Node->getValueType(0));
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// Figure out the register class to create for the destreg.
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// Note that if we're going to directly use an existing register,
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// it must be precisely the required class, and not a subclass
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// thereof.
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if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
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// Create the reg
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assert(SRC && "Couldn't find source register class");
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VRBase = MRI.createVirtualRegister(SRC);
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}
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// Create the insert_subreg or subreg_to_reg machine instruction.
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MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), TII->get(Opc));
|
|
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
|
|
|
|
// If creating a subreg_to_reg, then the first input operand
|
|
// is an implicit value immediate, otherwise it's a register
|
|
if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
|
|
const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
|
|
MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
|
|
} else
|
|
AddOperand(MI, N0, 0, 0, VRBaseMap);
|
|
// Add the subregster being inserted
|
|
AddOperand(MI, N1, 0, 0, VRBaseMap);
|
|
MI->addOperand(MachineOperand::CreateImm(SubIdx));
|
|
BB->insert(InsertPos, MI);
|
|
} else
|
|
llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
|
|
|
|
SDValue Op(Node, 0);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
|
|
isNew = isNew; // Silence compiler warning.
|
|
assert(isNew && "Node emitted out of order - early");
|
|
}
|
|
|
|
/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
|
|
/// COPY_TO_REGCLASS is just a normal copy, except that the destination
|
|
/// register is constrained to be in a particular register class.
|
|
///
|
|
void
|
|
ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap) {
|
|
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
|
|
const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
|
|
|
|
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
|
|
const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
|
|
|
|
// Create the new VReg in the destination class and emit a copy.
|
|
unsigned NewVReg = MRI.createVirtualRegister(DstRC);
|
|
bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
|
|
DstRC, SrcRC);
|
|
assert(Emitted &&
|
|
"Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
|
|
(void) Emitted;
|
|
|
|
SDValue Op(Node, 0);
|
|
bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
|
|
isNew = isNew; // Silence compiler warning.
|
|
assert(isNew && "Node emitted out of order - early");
|
|
}
|
|
|
|
/// EmitNode - Generate machine code for an node and needed dependencies.
|
|
///
|
|
void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
|
|
DenseMap<SDValue, unsigned> &VRBaseMap) {
|
|
// If machine instruction
|
|
if (Node->isMachineOpcode()) {
|
|
unsigned Opc = Node->getMachineOpcode();
|
|
|
|
// Handle subreg insert/extract specially
|
|
if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
|
|
Opc == TargetInstrInfo::INSERT_SUBREG ||
|
|
Opc == TargetInstrInfo::SUBREG_TO_REG) {
|
|
EmitSubregNode(Node, VRBaseMap);
|
|
return;
|
|
}
|
|
|
|
// Handle COPY_TO_REGCLASS specially.
|
|
if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) {
|
|
EmitCopyToRegClassNode(Node, VRBaseMap);
|
|
return;
|
|
}
|
|
|
|
if (Opc == TargetInstrInfo::IMPLICIT_DEF)
|
|
// We want a unique VR for each IMPLICIT_DEF use.
|
|
return;
|
|
|
|
const TargetInstrDesc &II = TII->get(Opc);
|
|
unsigned NumResults = CountResults(Node);
|
|
unsigned NodeOperands = CountOperands(Node);
|
|
unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
|
|
bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
|
|
II.getImplicitDefs() != 0;
|
|
#ifndef NDEBUG
|
|
unsigned NumMIOperands = NodeOperands + NumResults;
|
|
assert((II.getNumOperands() == NumMIOperands ||
|
|
HasPhysRegOuts || II.isVariadic()) &&
|
|
"#operands for dag node doesn't match .td file!");
|
|
#endif
|
|
|
|
// Create the new machine instruction.
|
|
MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), II);
|
|
|
|
// Add result register values for things that are defined by this
|
|
// instruction.
|
|
if (NumResults)
|
|
CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
|
|
|
|
// Emit all of the actual operands of this instruction, adding them to the
|
|
// instruction as appropriate.
|
|
bool HasOptPRefs = II.getNumDefs() > NumResults;
|
|
assert((!HasOptPRefs || !HasPhysRegOuts) &&
|
|
"Unable to cope with optional defs and phys regs defs!");
|
|
unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
|
|
for (unsigned i = NumSkip; i != NodeOperands; ++i)
|
|
AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
|
|
VRBaseMap);
|
|
|
|
// Emit all of the memory operands of this instruction
|
|
for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
|
|
AddMemOperand(MI,cast<MemOperandSDNode>(Node->getOperand(i+NumSkip))->MO);
|
|
|
|
if (II.usesCustomDAGSchedInsertionHook()) {
|
|
// Insert this instruction into the basic block using a target
|
|
// specific inserter which may returns a new basic block.
|
|
BB = TLI->EmitInstrWithCustomInserter(MI, BB);
|
|
InsertPos = BB->end();
|
|
} else {
|
|
BB->insert(InsertPos, MI);
|
|
}
|
|
|
|
// Additional results must be an physical register def.
|
|
if (HasPhysRegOuts) {
|
|
for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
|
|
unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
|
|
if (Node->hasAnyUseOfValue(i))
|
|
EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
switch (Node->getOpcode()) {
|
|
default:
|
|
#ifndef NDEBUG
|
|
Node->dump(DAG);
|
|
#endif
|
|
llvm_unreachable("This target-independent node should have been selected!");
|
|
break;
|
|
case ISD::EntryToken:
|
|
llvm_unreachable("EntryToken should have been excluded from the schedule!");
|
|
break;
|
|
case ISD::MERGE_VALUES:
|
|
case ISD::TokenFactor: // fall thru
|
|
break;
|
|
case ISD::CopyToReg: {
|
|
unsigned SrcReg;
|
|
SDValue SrcVal = Node->getOperand(2);
|
|
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
|
|
SrcReg = R->getReg();
|
|
else
|
|
SrcReg = getVR(SrcVal, VRBaseMap);
|
|
|
|
unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
|
|
break;
|
|
|
|
const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
|
|
// Get the register classes of the src/dst.
|
|
if (TargetRegisterInfo::isVirtualRegister(SrcReg))
|
|
SrcTRC = MRI.getRegClass(SrcReg);
|
|
else
|
|
SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(DestReg))
|
|
DstTRC = MRI.getRegClass(DestReg);
|
|
else
|
|
DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
|
|
Node->getOperand(1).getValueType());
|
|
|
|
bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
|
|
DstTRC, SrcTRC);
|
|
assert(Emitted && "Unable to issue a copy instruction!\n");
|
|
(void) Emitted;
|
|
break;
|
|
}
|
|
case ISD::CopyFromReg: {
|
|
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
|
|
break;
|
|
}
|
|
case ISD::INLINEASM: {
|
|
unsigned NumOps = Node->getNumOperands();
|
|
if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
|
|
--NumOps; // Ignore the flag operand.
|
|
|
|
// Create the inline asm machine instruction.
|
|
MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
|
|
TII->get(TargetInstrInfo::INLINEASM));
|
|
|
|
// Add the asm string as an external symbol operand.
|
|
const char *AsmStr =
|
|
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
|
|
MI->addOperand(MachineOperand::CreateES(AsmStr));
|
|
|
|
// Add all of the operand registers to the instruction.
|
|
for (unsigned i = 2; i != NumOps;) {
|
|
unsigned Flags =
|
|
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
|
|
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
|
|
|
|
MI->addOperand(MachineOperand::CreateImm(Flags));
|
|
++i; // Skip the ID value.
|
|
|
|
switch (Flags & 7) {
|
|
default: llvm_unreachable("Bad flags!");
|
|
case 2: // Def of register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, true));
|
|
}
|
|
break;
|
|
case 6: // Def of earlyclobber register.
|
|
for (; NumVals; --NumVals, ++i) {
|
|
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
|
|
MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
|
|
false, false, true));
|
|
}
|
|
break;
|
|
case 1: // Use of register.
|
|
case 3: // Immediate.
|
|
case 4: // Addressing mode.
|
|
// The addressing mode has been selected, just add all of the
|
|
// operands to the machine instruction.
|
|
for (; NumVals; --NumVals, ++i)
|
|
AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
|
|
break;
|
|
}
|
|
}
|
|
BB->insert(InsertPos, MI);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// EmitSchedule - Emit the machine code in scheduled order.
|
|
MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
|
|
DenseMap<SDValue, unsigned> VRBaseMap;
|
|
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
|
|
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
|
|
SUnit *SU = Sequence[i];
|
|
if (!SU) {
|
|
// Null SUnit* is a noop.
|
|
EmitNoop();
|
|
continue;
|
|
}
|
|
|
|
// For pre-regalloc scheduling, create instructions corresponding to the
|
|
// SDNode and any flagged SDNodes and append them to the block.
|
|
if (!SU->getNode()) {
|
|
// Emit a copy.
|
|
EmitPhysRegCopy(SU, CopyVRBaseMap);
|
|
continue;
|
|
}
|
|
|
|
SmallVector<SDNode *, 4> FlaggedNodes;
|
|
for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
|
|
N = N->getFlaggedNode())
|
|
FlaggedNodes.push_back(N);
|
|
while (!FlaggedNodes.empty()) {
|
|
EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
|
|
FlaggedNodes.pop_back();
|
|
}
|
|
EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
|
|
}
|
|
|
|
return BB;
|
|
}
|