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https://github.com/c64scene-ar/llvm-6502.git
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8ee1b65836
The NodeMetadata are maintained in an incremental way. When an edge between 2 nodes has its cost updated, in the course of graph reduction for example, the NodeMetadata need first to have the old edge cost removed, then the new edge cost added. Only once the NodeMetadata have been fully updated, it becomes safe to consider promoting the nodes to the ConservativelyAllocatable or OptimallyReducible sets. Previously, this promotion was occuring right after the removing the old cost, and this was breaking the assumption that a ConservativelyAllocatable should not be spilled. This patch also adds asserts to: - enforces the invariant that a node's reduction can not be downgraded, - only not provably allocatable or optimally reducible nodes can be spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228816 91177308-0d34-0410-b5e6-96231b3b80d8
384 lines
11 KiB
C++
384 lines
11 KiB
C++
//===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This file contains the AArch64 / Cortex-A57 specific register allocation
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// constraints for use by the PBQP register allocator.
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//
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// It is essentially a transcription of what is contained in
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// AArch64A57FPLoadBalancing, which tries to use a balanced
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// mix of odd and even D-registers when performing a critical sequence of
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// independent, non-quadword FP/ASIMD floating-point multiply-accumulates.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "aarch64-pbqp"
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#include "AArch64.h"
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#include "AArch64PBQPRegAlloc.h"
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#include "AArch64RegisterInfo.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegAllocPBQP.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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#ifndef NDEBUG
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bool isFPReg(unsigned reg) {
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return AArch64::FPR32RegClass.contains(reg) ||
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AArch64::FPR64RegClass.contains(reg) ||
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AArch64::FPR128RegClass.contains(reg);
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}
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#endif
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bool isOdd(unsigned reg) {
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switch (reg) {
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default:
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llvm_unreachable("Register is not from the expected class !");
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case AArch64::S1:
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case AArch64::S3:
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case AArch64::S5:
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case AArch64::S7:
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case AArch64::S9:
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case AArch64::S11:
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case AArch64::S13:
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case AArch64::S15:
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case AArch64::S17:
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case AArch64::S19:
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case AArch64::S21:
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case AArch64::S23:
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case AArch64::S25:
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case AArch64::S27:
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case AArch64::S29:
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case AArch64::S31:
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case AArch64::D1:
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case AArch64::D3:
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case AArch64::D5:
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case AArch64::D7:
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case AArch64::D9:
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case AArch64::D11:
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case AArch64::D13:
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case AArch64::D15:
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case AArch64::D17:
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case AArch64::D19:
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case AArch64::D21:
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case AArch64::D23:
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case AArch64::D25:
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case AArch64::D27:
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case AArch64::D29:
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case AArch64::D31:
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case AArch64::Q1:
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case AArch64::Q3:
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case AArch64::Q5:
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case AArch64::Q7:
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case AArch64::Q9:
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case AArch64::Q11:
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case AArch64::Q13:
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case AArch64::Q15:
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case AArch64::Q17:
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case AArch64::Q19:
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case AArch64::Q21:
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case AArch64::Q23:
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case AArch64::Q25:
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case AArch64::Q27:
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case AArch64::Q29:
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case AArch64::Q31:
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return true;
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case AArch64::S0:
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case AArch64::S2:
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case AArch64::S4:
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case AArch64::S6:
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case AArch64::S8:
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case AArch64::S10:
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case AArch64::S12:
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case AArch64::S14:
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case AArch64::S16:
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case AArch64::S18:
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case AArch64::S20:
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case AArch64::S22:
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case AArch64::S24:
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case AArch64::S26:
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case AArch64::S28:
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case AArch64::S30:
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case AArch64::D0:
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case AArch64::D2:
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case AArch64::D4:
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case AArch64::D6:
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case AArch64::D8:
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case AArch64::D10:
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case AArch64::D12:
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case AArch64::D14:
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case AArch64::D16:
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case AArch64::D18:
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case AArch64::D20:
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case AArch64::D22:
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case AArch64::D24:
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case AArch64::D26:
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case AArch64::D28:
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case AArch64::D30:
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case AArch64::Q0:
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case AArch64::Q2:
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case AArch64::Q4:
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case AArch64::Q6:
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case AArch64::Q8:
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case AArch64::Q10:
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case AArch64::Q12:
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case AArch64::Q14:
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case AArch64::Q16:
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case AArch64::Q18:
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case AArch64::Q20:
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case AArch64::Q22:
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case AArch64::Q24:
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case AArch64::Q26:
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case AArch64::Q28:
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case AArch64::Q30:
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return false;
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}
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}
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bool haveSameParity(unsigned reg1, unsigned reg2) {
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assert(isFPReg(reg1) && "Expecting an FP register for reg1");
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assert(isFPReg(reg2) && "Expecting an FP register for reg2");
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return isOdd(reg1) == isOdd(reg2);
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}
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}
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bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd,
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unsigned Ra) {
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if (Rd == Ra)
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return false;
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LiveIntervals &LIs = G.getMetadata().LIS;
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if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) {
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DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd)
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<< '\n');
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DEBUG(dbgs() << "Ra is a physical reg:" << TRI->isPhysicalRegister(Ra)
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<< '\n');
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return false;
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}
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PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
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PBQPRAGraph::NodeId node2 = G.getMetadata().getNodeIdForVReg(Ra);
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const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRdAllowed =
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&G.getNodeMetadata(node1).getAllowedRegs();
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const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRaAllowed =
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&G.getNodeMetadata(node2).getAllowedRegs();
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PBQPRAGraph::EdgeId edge = G.findEdge(node1, node2);
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// The edge does not exist. Create one with the appropriate interference
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// costs.
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if (edge == G.invalidEdgeId()) {
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const LiveInterval &ld = LIs.getInterval(Rd);
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const LiveInterval &la = LIs.getInterval(Ra);
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bool livesOverlap = ld.overlaps(la);
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PBQPRAGraph::RawMatrix costs(vRdAllowed->size() + 1,
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vRaAllowed->size() + 1, 0);
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for (unsigned i = 0, ie = vRdAllowed->size(); i != ie; ++i) {
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unsigned pRd = (*vRdAllowed)[i];
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for (unsigned j = 0, je = vRaAllowed->size(); j != je; ++j) {
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unsigned pRa = (*vRaAllowed)[j];
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if (livesOverlap && TRI->regsOverlap(pRd, pRa))
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costs[i + 1][j + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
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else
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costs[i + 1][j + 1] = haveSameParity(pRd, pRa) ? 0.0 : 1.0;
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}
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}
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G.addEdge(node1, node2, std::move(costs));
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return true;
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}
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if (G.getEdgeNode1Id(edge) == node2) {
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std::swap(node1, node2);
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std::swap(vRdAllowed, vRaAllowed);
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}
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// Enforce minCost(sameParity(RaClass)) > maxCost(otherParity(RdClass))
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PBQPRAGraph::RawMatrix costs(G.getEdgeCosts(edge));
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for (unsigned i = 0, ie = vRdAllowed->size(); i != ie; ++i) {
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unsigned pRd = (*vRdAllowed)[i];
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// Get the maximum cost (excluding unallocatable reg) for same parity
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// registers
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PBQP::PBQPNum sameParityMax = std::numeric_limits<PBQP::PBQPNum>::min();
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for (unsigned j = 0, je = vRaAllowed->size(); j != je; ++j) {
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unsigned pRa = (*vRaAllowed)[j];
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if (haveSameParity(pRd, pRa))
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if (costs[i + 1][j + 1] !=
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std::numeric_limits<PBQP::PBQPNum>::infinity() &&
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costs[i + 1][j + 1] > sameParityMax)
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sameParityMax = costs[i + 1][j + 1];
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}
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// Ensure all registers with a different parity have a higher cost
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// than sameParityMax
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for (unsigned j = 0, je = vRaAllowed->size(); j != je; ++j) {
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unsigned pRa = (*vRaAllowed)[j];
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if (!haveSameParity(pRd, pRa))
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if (sameParityMax > costs[i + 1][j + 1])
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costs[i + 1][j + 1] = sameParityMax + 1.0;
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}
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}
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G.updateEdgeCosts(edge, std::move(costs));
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return true;
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}
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void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
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unsigned Ra) {
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LiveIntervals &LIs = G.getMetadata().LIS;
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// Do some Chain management
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if (Chains.count(Ra)) {
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if (Rd != Ra) {
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DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to "
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<< PrintReg(Rd, TRI) << '\n';);
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Chains.remove(Ra);
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Chains.insert(Rd);
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}
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} else {
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DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI)
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<< '\n';);
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Chains.insert(Rd);
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}
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PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
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const LiveInterval &ld = LIs.getInterval(Rd);
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for (auto r : Chains) {
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// Skip self
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if (r == Rd)
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continue;
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const LiveInterval &lr = LIs.getInterval(r);
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if (ld.overlaps(lr)) {
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const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRdAllowed =
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&G.getNodeMetadata(node1).getAllowedRegs();
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PBQPRAGraph::NodeId node2 = G.getMetadata().getNodeIdForVReg(r);
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const PBQPRAGraph::NodeMetadata::AllowedRegVector *vRrAllowed =
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&G.getNodeMetadata(node2).getAllowedRegs();
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PBQPRAGraph::EdgeId edge = G.findEdge(node1, node2);
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assert(edge != G.invalidEdgeId() &&
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"PBQP error ! The edge should exist !");
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DEBUG(dbgs() << "Refining constraint !\n";);
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if (G.getEdgeNode1Id(edge) == node2) {
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std::swap(node1, node2);
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std::swap(vRdAllowed, vRrAllowed);
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}
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// Enforce that cost is higher with all other Chains of the same parity
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PBQP::Matrix costs(G.getEdgeCosts(edge));
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for (unsigned i = 0, ie = vRdAllowed->size(); i != ie; ++i) {
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unsigned pRd = (*vRdAllowed)[i];
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// Get the maximum cost (excluding unallocatable reg) for all other
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// parity registers
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PBQP::PBQPNum sameParityMax = std::numeric_limits<PBQP::PBQPNum>::min();
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for (unsigned j = 0, je = vRrAllowed->size(); j != je; ++j) {
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unsigned pRa = (*vRrAllowed)[j];
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if (!haveSameParity(pRd, pRa))
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if (costs[i + 1][j + 1] !=
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std::numeric_limits<PBQP::PBQPNum>::infinity() &&
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costs[i + 1][j + 1] > sameParityMax)
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sameParityMax = costs[i + 1][j + 1];
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}
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// Ensure all registers with same parity have a higher cost
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// than sameParityMax
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for (unsigned j = 0, je = vRrAllowed->size(); j != je; ++j) {
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unsigned pRa = (*vRrAllowed)[j];
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if (haveSameParity(pRd, pRa))
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if (sameParityMax > costs[i + 1][j + 1])
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costs[i + 1][j + 1] = sameParityMax + 1.0;
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}
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}
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G.updateEdgeCosts(edge, std::move(costs));
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}
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}
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}
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static bool regJustKilledBefore(const LiveIntervals &LIs, unsigned reg,
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const MachineInstr &MI) {
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LiveInterval LI = LIs.getInterval(reg);
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SlotIndex SI = LIs.getInstructionIndex(&MI);
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return LI.expiredAt(SI);
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}
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void A57ChainingConstraint::apply(PBQPRAGraph &G) {
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const MachineFunction &MF = G.getMetadata().MF;
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LiveIntervals &LIs = G.getMetadata().LIS;
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TRI = MF.getSubtarget().getRegisterInfo();
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DEBUG(MF.dump());
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for (const auto &MBB: MF) {
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Chains.clear(); // FIXME: really needed ? Could not work at MF level ?
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for (const auto &MI: MBB) {
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// Forget Chains which have expired
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for (auto r : Chains) {
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SmallVector<unsigned, 8> toDel;
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if(regJustKilledBefore(LIs, r, MI)) {
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DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at ";
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MI.print(dbgs()););
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toDel.push_back(r);
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}
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while (!toDel.empty()) {
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Chains.remove(toDel.back());
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toDel.pop_back();
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}
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}
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switch (MI.getOpcode()) {
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case AArch64::FMSUBSrrr:
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case AArch64::FMADDSrrr:
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case AArch64::FNMSUBSrrr:
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case AArch64::FNMADDSrrr:
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case AArch64::FMSUBDrrr:
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case AArch64::FMADDDrrr:
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case AArch64::FNMSUBDrrr:
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case AArch64::FNMADDDrrr: {
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unsigned Rd = MI.getOperand(0).getReg();
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unsigned Ra = MI.getOperand(3).getReg();
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if (addIntraChainConstraint(G, Rd, Ra))
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addInterChainConstraint(G, Rd, Ra);
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break;
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}
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case AArch64::FMLAv2f32:
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case AArch64::FMLSv2f32: {
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unsigned Rd = MI.getOperand(0).getReg();
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addInterChainConstraint(G, Rd, Rd);
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break;
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}
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default:
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break;
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}
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}
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}
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}
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