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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
4.3 KiB
TableGen
105 lines
4.3 KiB
TableGen
//==-- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Define TII for use in SchedVariant Predicates.
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// const MachineInstr *MI and const TargetSchedModel *SchedModel
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// are defined by default.
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def : PredicateProlog<[{
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const AArch64InstrInfo *TII =
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static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
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(void)TII;
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}]>;
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// AArch64 Scheduler Definitions
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def WriteImm : SchedWrite; // MOVN, MOVZ
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// TODO: Provide variants for MOV32/64imm Pseudos that dynamically
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// select the correct sequence of WriteImms.
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def WriteI : SchedWrite; // ALU
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def WriteISReg : SchedWrite; // ALU of Shifted-Reg
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def WriteIEReg : SchedWrite; // ALU of Extended-Reg
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def ReadI : SchedRead; // ALU
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def ReadISReg : SchedRead; // ALU of Shifted-Reg
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def ReadIEReg : SchedRead; // ALU of Extended-Reg
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def WriteExtr : SchedWrite; // EXTR shifts a reg pair
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def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
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def WriteIS : SchedWrite; // Shift/Scale
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def WriteID32 : SchedWrite; // 32-bit Divide
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def WriteID64 : SchedWrite; // 64-bit Divide
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def ReadID : SchedRead; // 32/64-bit Divide
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def WriteIM32 : SchedWrite; // 32-bit Multiply
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def WriteIM64 : SchedWrite; // 64-bit Multiply
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def ReadIM : SchedRead; // 32/64-bit Multiply
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def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate
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def WriteBr : SchedWrite; // Branch
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def WriteBrReg : SchedWrite; // Indirect Branch
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def WriteLD : SchedWrite; // Load from base addr plus immediate offset
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def WriteST : SchedWrite; // Store to base addr plus immediate offset
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def WriteSTP : SchedWrite; // Store a register pair.
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def WriteAdr : SchedWrite; // Address pre/post increment.
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def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).
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def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
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def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
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// Predicate for determining when a shiftable register is shifted.
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def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(MI)}]>;
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// Predicate for determining when a extendedable register is extended.
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def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(MI)}]>;
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// ScaledIdxPred is true if a WriteLDIdx operand will be
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// scaled. Subtargets can use this to dynamically select resources and
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// latency for WriteLDIdx and ReadAdrBase.
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def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(MI)}]>;
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// Serialized two-level address load.
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// EXAMPLE: LOADGot
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def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
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// Serialized two-level address lookup.
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// EXAMPLE: MOVaddr...
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def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>;
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// The second register of a load-pair.
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// LDP,LDPSW,LDNP,LDXP,LDAXP
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def WriteLDHi : SchedWrite;
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// Store-exclusive is a store followed by a dependent load.
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def WriteSTX : WriteSequence<[WriteST, WriteLD]>;
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def WriteSys : SchedWrite; // Long, variable latency system ops.
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def WriteBarrier : SchedWrite; // Memory barrier.
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def WriteHint : SchedWrite; // Hint instruction.
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def WriteF : SchedWrite; // General floating-point ops.
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def WriteFCmp : SchedWrite; // Floating-point compare.
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def WriteFCvt : SchedWrite; // Float conversion.
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def WriteFCopy : SchedWrite; // Float-int register copy.
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def WriteFImm : SchedWrite; // Floating-point immediate.
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def WriteFMul : SchedWrite; // Floating-point multiply.
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def WriteFDiv : SchedWrite; // Floating-point division.
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def WriteV : SchedWrite; // Vector ops.
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def WriteVLD : SchedWrite; // Vector loads.
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def WriteVST : SchedWrite; // Vector stores.
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// Read the unwritten lanes of the VLD's destination registers.
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def ReadVLD : SchedRead;
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// Sequential vector load and shuffle.
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def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>;
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def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>;
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// Store a shuffled vector.
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def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>;
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def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>;
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