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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120982 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
5.3 KiB
TableGen
143 lines
5.3 KiB
TableGen
//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the PTX instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "PTXInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
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if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
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return PT->getAddressSpace() <= 255;
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return false;
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}]>;
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// Addressing modes.
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def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
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def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
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// Address operands
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def MEMri : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops RRegs32, i32imm);
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}
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def MEMii : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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//===----------------------------------------------------------------------===//
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// PTX Specific Node Definitions
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//===----------------------------------------------------------------------===//
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// PTX allow generic 3-reg shifts like shl r0, r1, r2
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def PTXshl : SDNode<"ISD::SHL", SDTIntBinOp>;
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def PTXsrl : SDNode<"ISD::SRL", SDTIntBinOp>;
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def PTXsra : SDNode<"ISD::SRA", SDTIntBinOp>;
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def PTXexit
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: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
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def PTXret
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: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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multiclass INT3<string opcstr, SDNode opnode> {
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def rr : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, RRegs32:$b),
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!strconcat(opcstr, ".%type\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
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def ri : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, i32imm:$b),
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!strconcat(opcstr, ".%type\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
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}
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// no %type directive, non-communtable
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multiclass INT3ntnc<string opcstr, SDNode opnode> {
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def rr : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, RRegs32:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
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def ri : InstPTX<(outs RRegs32:$d),
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(ins RRegs32:$a, i32imm:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
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def ir : InstPTX<(outs RRegs32:$d),
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(ins i32imm:$a, RRegs32:$b),
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!strconcat(opcstr, "\t$d, $a, $b"),
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[(set RRegs32:$d, (opnode imm:$a, RRegs32:$b))]>;
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}
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multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
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def ri : InstPTX<(outs RC:$d),
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(ins MEMri:$a),
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!strconcat(opstr, ".%type\t$d, [$a]"),
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[(set RC:$d, (pat_load ADDRri:$a))]>;
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def ii : InstPTX<(outs RC:$d),
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(ins MEMii:$a),
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!strconcat(opstr, ".%type\t$d, [$a]"),
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[(set RC:$d, (pat_load ADDRii:$a))]>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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///===- Integer Arithmetic Instructions -----------------------------------===//
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defm ADD : INT3<"add", add>;
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defm SUB : INT3<"sub", sub>;
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///===- Logic and Shift Instructions --------------------------------------===//
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defm SHL : INT3ntnc<"shl.b32", PTXshl>;
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defm SRL : INT3ntnc<"shr.u32", PTXsrl>;
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defm SRA : INT3ntnc<"shr.s32", PTXsra>;
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///===- Data Movement and Conversion Instructions -------------------------===//
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let neverHasSideEffects = 1 in {
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// rely on isMoveInstr to separate MOVpp, MOVrr, etc.
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def MOVpp
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: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
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def MOVrr
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: InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
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}
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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def MOVpi
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: InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
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[(set Preds:$d, imm:$a)]>;
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def MOVri
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: InstPTX<(outs RRegs32:$d), (ins i32imm:$a), "mov.s32\t$d, $a",
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[(set RRegs32:$d, imm:$a)]>;
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}
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defm LDg : PTX_LD<"ld.global", RRegs32, load_global>;
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///===- Control Flow Instructions -----------------------------------------===//
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
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def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
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}
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