mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b48f2c2e1d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116805 91177308-0d34-0410-b5e6-96231b3b80d8
103 lines
3.1 KiB
TableGen
103 lines
3.1 KiB
TableGen
//===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class PTXReg<string n> : Register<n> {
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let Namespace = "PTX";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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def P0 : PTXReg<"p0">;
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def P1 : PTXReg<"p1">;
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def P2 : PTXReg<"p2">;
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def P3 : PTXReg<"p3">;
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def P4 : PTXReg<"p4">;
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def P5 : PTXReg<"p5">;
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def P6 : PTXReg<"p6">;
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def P7 : PTXReg<"p7">;
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def P8 : PTXReg<"p8">;
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def P9 : PTXReg<"p9">;
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def P10 : PTXReg<"p10">;
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def P11 : PTXReg<"p11">;
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def P12 : PTXReg<"p12">;
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def P13 : PTXReg<"p13">;
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def P14 : PTXReg<"p14">;
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def P15 : PTXReg<"p15">;
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def P16 : PTXReg<"p16">;
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def P17 : PTXReg<"p17">;
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def P18 : PTXReg<"p18">;
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def P19 : PTXReg<"p19">;
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def P20 : PTXReg<"p20">;
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def P21 : PTXReg<"p21">;
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def P22 : PTXReg<"p22">;
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def P23 : PTXReg<"p23">;
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def P24 : PTXReg<"p24">;
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def P25 : PTXReg<"p25">;
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def P26 : PTXReg<"p26">;
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def P27 : PTXReg<"p27">;
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def P28 : PTXReg<"p28">;
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def P29 : PTXReg<"p29">;
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def P30 : PTXReg<"p30">;
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def P31 : PTXReg<"p31">;
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def R0 : PTXReg<"r0">;
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def R1 : PTXReg<"r1">;
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def R2 : PTXReg<"r2">;
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def R3 : PTXReg<"r3">;
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def R4 : PTXReg<"r4">;
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def R5 : PTXReg<"r5">;
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def R6 : PTXReg<"r6">;
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def R7 : PTXReg<"r7">;
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def R8 : PTXReg<"r8">;
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def R9 : PTXReg<"r9">;
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def R10 : PTXReg<"r10">;
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def R11 : PTXReg<"r11">;
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def R12 : PTXReg<"r12">;
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def R13 : PTXReg<"r13">;
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def R14 : PTXReg<"r14">;
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def R15 : PTXReg<"r15">;
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def R16 : PTXReg<"r16">;
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def R17 : PTXReg<"r17">;
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def R18 : PTXReg<"r18">;
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def R19 : PTXReg<"r19">;
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def R20 : PTXReg<"r20">;
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def R21 : PTXReg<"r21">;
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def R22 : PTXReg<"r22">;
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def R23 : PTXReg<"r23">;
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def R24 : PTXReg<"r24">;
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def R25 : PTXReg<"r25">;
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def R26 : PTXReg<"r26">;
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def R27 : PTXReg<"r27">;
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def R28 : PTXReg<"r28">;
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def R29 : PTXReg<"r29">;
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def R30 : PTXReg<"r30">;
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def R31 : PTXReg<"r31">;
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def Preds : RegisterClass<"PTX", [i1], 8,
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[P0, P1, P2, P3, P4, P5, P6, P7,
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P8, P9, P10, P11, P12, P13, P14, P15,
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P16, P17, P18, P19, P20, P21, P22, P23,
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P24, P25, P26, P27, P28, P29, P30, P31]>;
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def RRegs32 : RegisterClass<"PTX", [i32], 32,
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[R0, R1, R2, R3, R4, R5, R6, R7,
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R8, R9, R10, R11, R12, R13, R14, R15,
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R16, R17, R18, R19, R20, R21, R22, R23,
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R24, R25, R26, R27, R28, R29, R30, R31]>;
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