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8604e75721
make them return void. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11447 91177308-0d34-0410-b5e6-96231b3b80d8
306 lines
13 KiB
C++
306 lines
13 KiB
C++
//===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MREGISTERINFO_H
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#define LLVM_TARGET_MREGISTERINFO_H
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#include <cassert>
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#include "llvm/CodeGen/MachineBasicBlock.h"
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namespace llvm {
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class Type;
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class MachineFunction;
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class MachineInstr;
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/// MRegisterDesc - This record contains all of the information known about a
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/// particular register. The AliasSet field (if not null) contains a pointer to
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/// a Zero terminated array of registers that this register aliases. This is
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/// needed for architectures like X86 which have AL alias AX alias EAX.
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/// Registers that this does not apply to simply should set this to null.
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///
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struct MRegisterDesc {
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const char *Name; // Assembly language name for the register
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const unsigned *AliasSet; // Register Alias Set, described above
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unsigned Flags; // Flags identifying register properties (below)
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unsigned TSFlags; // Target Specific Flags
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};
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class TargetRegisterClass {
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public:
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typedef const unsigned* iterator;
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typedef const unsigned* const_iterator;
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private:
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const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
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const iterator RegsBegin, RegsEnd;
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public:
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TargetRegisterClass(unsigned RS, unsigned Al, iterator RB, iterator RE)
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: RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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// begin/end - Return all of the registers in this class.
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iterator begin() const { return RegsBegin; }
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iterator end() const { return RegsEnd; }
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// getNumRegs - Return the number of registers in this class
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unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
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// getRegister - Return the specified register in the class
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unsigned getRegister(unsigned i) const {
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assert(i < getNumRegs() && "Register number out of range!");
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return RegsBegin[i];
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}
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/// allocation_order_begin/end - These methods define a range of registers
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/// which specify the registers in this class that are valid to register
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/// allocate, and the preferred order to allocate them in. For example,
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/// callee saved registers should be at the end of the list, because it is
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/// cheaper to allocate caller saved registers.
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///
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/// These methods take a MachineFunction argument, which can be used to tune
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/// the allocatable registers based on the characteristics of the function.
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/// One simple example is that the frame pointer register can be used if
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/// frame-pointer-elimination is performed.
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///
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/// By default, these methods return all registers in the class.
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///
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virtual iterator allocation_order_begin(MachineFunction &MF) const {
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return begin();
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}
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virtual iterator allocation_order_end(MachineFunction &MF) const {
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return end();
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return RegSize; }
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/// getAlignment - Return the minimum required alignment for a register of
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/// this class.
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unsigned getAlignment() const { return Alignment; }
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};
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/// MRegisterInfo base class - We assume that the target defines a static array
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/// of MRegisterDesc objects that represent all of the machine registers that
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/// the target has. As such, we simply have to track a pointer to this array so
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/// that we can turn register number into a register descriptor.
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///
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class MRegisterInfo {
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public:
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typedef const TargetRegisterClass * const * regclass_iterator;
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private:
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const MRegisterDesc *Desc; // Pointer to the descriptor array
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unsigned NumRegs; // Number of entries in the array
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regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
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const TargetRegisterClass **PhysRegClasses; // Reg class for each register
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int CallFrameSetupOpcode, CallFrameDestroyOpcode;
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protected:
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MRegisterInfo(const MRegisterDesc *D, unsigned NR,
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regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
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int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
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virtual ~MRegisterInfo();
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public:
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enum { // Define some target independent constants
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/// NoRegister - This 'hard' register is a 'noop' register for all backends.
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/// This is used as the destination register for instructions that do not
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/// produce a value. Some frontends may use this as an operand register to
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/// mean special things, for example, the Sparc backend uses R0 to mean %g0
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/// which always PRODUCES the value 0. The X86 backend does not use this
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/// value as an operand register, except for memory references.
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///
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NoRegister = 0,
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/// FirstVirtualRegister - This is the first register number that is
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/// considered to be a 'virtual' register, which is part of the SSA
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/// namespace. This must be the same for all targets, which means that each
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/// target is limited to 1024 registers.
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///
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FirstVirtualRegister = 1024,
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};
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/// isPhysicalRegister - Return true if the specified register number is in
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/// the physical register namespace.
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static bool isPhysicalRegister(unsigned Reg) {
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return Reg < FirstVirtualRegister;
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}
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/// isVirtualRegister - Return true if the specified register number is in
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/// the virtual register namespace.
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static bool isVirtualRegister(unsigned Reg) {
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return Reg >= FirstVirtualRegister;
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}
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const MRegisterDesc &operator[](unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to access record for invalid register number!");
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return Desc[RegNo];
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}
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/// Provide a get method, equivalent to [], but more useful if we have a
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/// pointer to this object.
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///
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const MRegisterDesc &get(unsigned RegNo) const { return operator[](RegNo); }
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/// getRegClass - Return the register class for the specified physical
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/// register.
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///
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const TargetRegisterClass *getRegClass(unsigned RegNo) const {
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assert(RegNo < NumRegs && "Register number out of range!");
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assert(PhysRegClasses[RegNo] && "Register is not in a class!");
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return PhysRegClasses[RegNo];
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}
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/// getAliasSet - Return the set of registers aliased by the specified
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/// register, or a null list of there are none. The list returned is zero
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/// terminated.
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///
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const unsigned *getAliasSet(unsigned RegNo) const {
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return get(RegNo).AliasSet;
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}
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/// getName - Return the symbolic target specific name for the specified
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/// physical register.
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const char *getName(unsigned RegNo) const {
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return get(RegNo).Name;
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}
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/// getNumRegs - Return the number of registers this target has
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/// (useful for sizing arrays holding per register information)
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unsigned getNumRegs() const {
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return NumRegs;
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}
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virtual const unsigned* getCalleeSaveRegs() const = 0;
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//===--------------------------------------------------------------------===//
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// Register Class Information
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//
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/// Register class iterators
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///
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regclass_iterator regclass_begin() const { return RegClassBegin; }
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regclass_iterator regclass_end() const { return RegClassEnd; }
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unsigned getNumRegClasses() const {
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return regclass_end()-regclass_begin();
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}
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//===--------------------------------------------------------------------===//
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// All basic block modifier functions below return the number of
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// instructions added to (negative if removed from) the basic block
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// passed as their first argument.
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//
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// FIXME: This is only needed because we use a std::vector instead
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// of an ilist to keep MachineBasicBlock instructions. Inserting an
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// instruction to a MachineBasicBlock invalidates all iterators to
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// the basic block. The return value can be used to update an index
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// to the machine basic block instruction vector and circumvent the
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// iterator elimination problem but this is really not needed if we
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// move to a better representation.
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//
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//===--------------------------------------------------------------------===//
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// Interfaces used by the register allocator and stack frame
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// manipulation passes to move data around between registers,
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// immediates and memory. The return value is the number of
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// instructions added to (negative if removed from) the basic block.
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//
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virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const = 0;
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virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const = 0;
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virtual int copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const = 0;
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/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
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/// frame setup/destroy instructions if they exist (-1 otherwise). Some
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/// targets use pseudo instructions in order to abstract away the difference
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/// between operating with a frame pointer and operating without, through the
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/// use of these two instructions.
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///
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int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
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int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
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/// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
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/// code insertion to eliminate call frame setup and destroy pseudo
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/// instructions (but only if the Target is using them). It is responsible
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/// for eliminating these instructions, replacing them with concrete
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/// instructions. This method need only be implemented if using call frame
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/// setup/destroy pseudo instructions. The return value is the number of
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/// instructions added to (negative if removed from) the basic block.
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///
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virtual void
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
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"eliminateCallFramePseudoInstr must be implemented if using"
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" call frame setup/destroy pseudo instructions!");
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assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
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}
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/// processFunctionBeforeFrameFinalized - This method is called immediately
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/// before the specified functions frame layout (MF.getFrameInfo()) is
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/// finalized. Once the frame is finalized, MO_FrameIndex operands are
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/// replaced with direct constants. This method is optional. The return value
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/// is the number of instructions added to (negative if removed from) the
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/// basic block
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///
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virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
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}
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/// eliminateFrameIndex - This method must be overriden to eliminate abstract
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/// frame indices from instructions which may use them. The instruction
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/// referenced by the iterator contains an MO_FrameIndex operand which must be
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/// eliminated by this method. This method may modify or replace the
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/// specified instruction, as long as it keeps the iterator pointing the the
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/// finished product. The return value is the number of instructions
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/// added to (negative if removed from) the basic block.
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///
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virtual void eliminateFrameIndex(MachineFunction &MF,
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MachineBasicBlock::iterator MI) const = 0;
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function. The return value is the number of instructions
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/// added to (negative if removed from) the basic block (entry for prologue).
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///
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virtual void emitPrologue(MachineFunction &MF) const = 0;
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virtual void emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const = 0;
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};
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} // End llvm namespace
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#endif
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