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ab8672c8bb
MachineBasicBlock. Also change opcode to a short and numImplicitRefs to an unsigned char so that overall MachineInstr's size stays the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11357 91177308-0d34-0410-b5e6-96231b3b80d8
433 lines
16 KiB
C++
433 lines
16 KiB
C++
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instructions to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "Support/DataTypes.h"
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#include <vector>
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#include <cassert>
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namespace llvm {
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class MachineInstr;
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class TargetMachine;
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class Value;
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class Type;
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class Instruction;
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class Constant;
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class Function;
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class MachineCodeForInstruction;
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//---------------------------------------------------------------------------
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// Data types used to define information about a single machine instruction
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//---------------------------------------------------------------------------
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typedef short MachineOpCode;
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typedef unsigned InstrSchedClass;
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const MachineOpCode INVALID_MACHINE_OPCODE = -1;
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//---------------------------------------------------------------------------
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// struct TargetInstrDescriptor:
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// Predefined information about each machine instruction.
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// Designed to initialized statically.
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//
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const unsigned M_NOP_FLAG = 1 << 0;
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const unsigned M_BRANCH_FLAG = 1 << 1;
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const unsigned M_CALL_FLAG = 1 << 2;
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const unsigned M_RET_FLAG = 1 << 3;
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const unsigned M_ARITH_FLAG = 1 << 4;
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const unsigned M_CC_FLAG = 1 << 6;
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const unsigned M_LOGICAL_FLAG = 1 << 6;
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const unsigned M_INT_FLAG = 1 << 7;
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const unsigned M_FLOAT_FLAG = 1 << 8;
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const unsigned M_CONDL_FLAG = 1 << 9;
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const unsigned M_LOAD_FLAG = 1 << 10;
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const unsigned M_PREFETCH_FLAG = 1 << 11;
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const unsigned M_STORE_FLAG = 1 << 12;
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const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
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const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
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// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
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const unsigned M_2_ADDR_FLAG = 1 << 15;
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// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
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// block? Typically this is things like return and branch instructions.
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// Various passes use this to insert code into the bottom of a basic block, but
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// before control flow occurs.
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const unsigned M_TERMINATOR_FLAG = 1 << 16;
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struct TargetInstrDescriptor {
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const char * Name; // Assembly language mnemonic for the opcode.
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int numOperands; // Number of args; -1 if variable #args
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int resultPos; // Position of the result; -1 if no result
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unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
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bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
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// smallest -ve value is -(maxImmedConst+1).
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unsigned numDelaySlots; // Number of delay slots after instruction
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unsigned latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned Flags; // flags identifying machine instr class
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unsigned TSFlags; // Target Specific Flag values
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const unsigned *ImplicitUses; // Registers implicitly read by this instr
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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};
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//---------------------------------------------------------------------------
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///
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/// TargetInstrInfo - Interface to description of machine instructions
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///
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class TargetInstrInfo {
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const TargetInstrDescriptor* desc; // raw array to allow static init'n
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unsigned descSize; // number of entries in the desc array
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unsigned numRealOpCodes; // number of non-dummy op codes
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
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unsigned numRealOpCodes);
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virtual ~TargetInstrInfo();
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// Invariant: All instruction sets use opcode #0 as the PHI instruction
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enum { PHI = 0 };
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unsigned getNumRealOpCodes() const { return numRealOpCodes; }
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unsigned getNumTotalOpCodes() const { return descSize; }
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const TargetInstrDescriptor& get(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int)descSize);
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return desc[opCode];
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}
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const char *getName(MachineOpCode opCode) const {
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return get(opCode).Name;
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}
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int getNumOperands(MachineOpCode opCode) const {
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return get(opCode).numOperands;
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}
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int getResultPos(MachineOpCode opCode) const {
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return get(opCode).resultPos;
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}
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unsigned getNumDelaySlots(MachineOpCode opCode) const {
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return get(opCode).numDelaySlots;
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}
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InstrSchedClass getSchedClass(MachineOpCode opCode) const {
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return get(opCode).schedClass;
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}
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const unsigned *getImplicitUses(MachineOpCode opCode) const {
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return get(opCode).ImplicitUses;
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}
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const unsigned *getImplicitDefs(MachineOpCode opCode) const {
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return get(opCode).ImplicitDefs;
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}
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//
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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bool isNop(MachineOpCode opCode) const {
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return get(opCode).Flags & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return get(opCode).Flags & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return get(opCode).Flags & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return get(opCode).Flags & M_BRANCH_FLAG
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|| get(opCode).Flags & M_CALL_FLAG
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|| get(opCode).Flags & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return get(opCode).Flags & M_ARITH_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return get(opCode).Flags & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return get(opCode).Flags & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return get(opCode).Flags & M_LOAD_FLAG
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|| get(opCode).Flags & M_PREFETCH_FLAG
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|| get(opCode).Flags & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_DUMMY_PHI_FLAG;
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}
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bool isPseudoInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_PSEUDO_FLAG;
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}
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bool isTwoAddrInstr(MachineOpCode opCode) const {
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return get(opCode).Flags & M_2_ADDR_FLAG;
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}
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bool isTerminatorInstr(unsigned Opcode) const {
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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return false;
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}
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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// before the results are ready.
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// Default to true since most instructions on many architectures allow this.
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//
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virtual bool hasOperandInterlock(MachineOpCode opCode) const {
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return true;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const {
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return true;
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}
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//
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// Latencies for individual instructions and instruction pairs
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//
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virtual int minLatency(MachineOpCode opCode) const {
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return get(opCode).latency;
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}
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virtual int maxLatency(MachineOpCode opCode) const {
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return get(opCode).latency;
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}
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//
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// Which operand holds an immediate constant? Returns -1 if none
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//
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virtual int getImmedConstantPos(MachineOpCode opCode) const {
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return -1; // immediate position is machine specific, so say -1 == "none"
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}
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// Check if the specified constant fits in the immediate field
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// of this machine instruction
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//
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virtual bool constantFitsInImmedField(MachineOpCode opCode,
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int64_t intValue) const;
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// Return the largest positive constant that can be held in the IMMED field
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// of this machine instruction.
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// isSignExtended is set to true if the value is sign-extended before use
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// (this is true for all immediate fields in SPARC instructions).
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// Return 0 if the instruction has no IMMED field.
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//
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virtual uint64_t maxImmedConstant(MachineOpCode opCode,
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bool &isSignExtended) const {
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isSignExtended = get(opCode).immedIsSignExtended;
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return get(opCode).maxImmedConst;
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}
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//-------------------------------------------------------------------------
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// Queries about representation of LLVM quantities (e.g., constants)
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//-------------------------------------------------------------------------
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/// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
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/// from memory into a register, i.e., cannot be set bitwise in register and
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/// cannot use immediate fields of instructions. Note that this only makes
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/// sense for primitive types.
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///
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virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
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// Test if this constant may not fit in the immediate field of the
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// machine instructions (probably) generated for this instruction.
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//
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virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
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const Instruction* I) const {
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return true; // safe but very conservative
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}
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
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///
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virtual MachineInstr* createNOPinstr() const = 0;
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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virtual bool isNOPinstr(const MachineInstr &MI) const = 0;
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//
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// WARNING: These methods are Sparc specific
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//
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//-------------------------------------------------------------------------
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// Get certain common op codes for the current target. this and all the
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// Create* methods below should be moved to a machine code generation class
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//
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virtual MachineOpCode getNOPOpCode() const { abort(); }
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// Get the value of an integral constant in the form that must
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// be put into the machine register. The specified constant is interpreted
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// as (i.e., converted if necessary to) the specified destination type. The
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// result is always returned as an uint64_t, since the representation of
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// int64_t and uint64_t are identical. The argument can be any known const.
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//
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// isValidConstant is set to true if a valid constant was found.
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//
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virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
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const Value *V,
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const Type *destType,
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bool &isValidConstant) const {
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abort();
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}
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Symbolic constants or constants that must be accessed from memory
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// are added to the constant pool via MachineFunction::get(F).
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//
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virtual void CreateCodeToLoadConst(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const {
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abort();
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}
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateSignExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& MI) const {
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abort();
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}
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// Create instruction sequence to produce a zero-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned srcSizeInBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const {
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abort();
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}
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};
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} // End llvm namespace
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#endif
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