mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-30 19:29:20 +00:00
7e99a60857
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
87 lines
2.5 KiB
C++
87 lines
2.5 KiB
C++
//===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the ARM implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "ARMInstrInfo.h"
|
|
#include "ARM.h"
|
|
#include "ARMMachineFunctionInfo.h"
|
|
#include "MCTargetDesc/ARMAddressingModes.h"
|
|
#include "llvm/ADT/STLExtras.h"
|
|
#include "llvm/CodeGen/LiveVariables.h"
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/CodeGen/MachineJumpTableInfo.h"
|
|
#include "llvm/MC/MCAsmInfo.h"
|
|
#include "llvm/MC/MCInst.h"
|
|
using namespace llvm;
|
|
|
|
ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
|
|
: ARMBaseInstrInfo(STI), RI(*this, STI) {
|
|
}
|
|
|
|
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
|
|
void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
|
|
if (hasNOP()) {
|
|
NopInst.setOpcode(ARM::HINT);
|
|
NopInst.addOperand(MCOperand::CreateImm(0));
|
|
NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
NopInst.addOperand(MCOperand::CreateReg(0));
|
|
} else {
|
|
NopInst.setOpcode(ARM::MOVr);
|
|
NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
NopInst.addOperand(MCOperand::CreateReg(0));
|
|
NopInst.addOperand(MCOperand::CreateReg(0));
|
|
}
|
|
}
|
|
|
|
unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
|
|
switch (Opc) {
|
|
default: break;
|
|
case ARM::LDR_PRE_IMM:
|
|
case ARM::LDR_PRE_REG:
|
|
case ARM::LDR_POST_IMM:
|
|
case ARM::LDR_POST_REG:
|
|
return ARM::LDRi12;
|
|
case ARM::LDRH_PRE:
|
|
case ARM::LDRH_POST:
|
|
return ARM::LDRH;
|
|
case ARM::LDRB_PRE_IMM:
|
|
case ARM::LDRB_PRE_REG:
|
|
case ARM::LDRB_POST_IMM:
|
|
case ARM::LDRB_POST_REG:
|
|
return ARM::LDRBi12;
|
|
case ARM::LDRSH_PRE:
|
|
case ARM::LDRSH_POST:
|
|
return ARM::LDRSH;
|
|
case ARM::LDRSB_PRE:
|
|
case ARM::LDRSB_POST:
|
|
return ARM::LDRSB;
|
|
case ARM::STR_PRE_IMM:
|
|
case ARM::STR_PRE_REG:
|
|
case ARM::STR_POST_IMM:
|
|
case ARM::STR_POST_REG:
|
|
return ARM::STRi12;
|
|
case ARM::STRH_PRE:
|
|
case ARM::STRH_POST:
|
|
return ARM::STRH;
|
|
case ARM::STRB_PRE_IMM:
|
|
case ARM::STRB_PRE_REG:
|
|
case ARM::STRB_POST_IMM:
|
|
case ARM::STRB_POST_REG:
|
|
return ARM::STRBi12;
|
|
}
|
|
|
|
return 0;
|
|
}
|