mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
d04a8d4b33
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
358 lines
12 KiB
C++
358 lines
12 KiB
C++
//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInstrInfo.h"
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#include "Sparc.h"
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#include "SparcMachineFunctionInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_CTOR
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#include "SparcGenInstrInfo.inc"
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using namespace llvm;
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SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
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: SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
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RI(ST, *this), Subtarget(ST) {
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::LDri ||
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MI->getOpcode() == SP::LDFri ||
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MI->getOpcode() == SP::LDDFri) {
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if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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if (MI->getOpcode() == SP::STri ||
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MI->getOpcode() == SP::STFri ||
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MI->getOpcode() == SP::STDFri) {
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if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
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MI->getOperand(1).getImm() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(2).getReg();
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}
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}
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return 0;
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}
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static bool IsIntegerCC(unsigned CC)
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{
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return (CC <= SPCC::ICC_VC);
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}
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static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
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{
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switch(CC) {
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case SPCC::ICC_NE: return SPCC::ICC_E;
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case SPCC::ICC_E: return SPCC::ICC_NE;
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case SPCC::ICC_G: return SPCC::ICC_LE;
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case SPCC::ICC_LE: return SPCC::ICC_G;
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case SPCC::ICC_GE: return SPCC::ICC_L;
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case SPCC::ICC_L: return SPCC::ICC_GE;
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case SPCC::ICC_GU: return SPCC::ICC_LEU;
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case SPCC::ICC_LEU: return SPCC::ICC_GU;
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case SPCC::ICC_CC: return SPCC::ICC_CS;
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case SPCC::ICC_CS: return SPCC::ICC_CC;
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case SPCC::ICC_POS: return SPCC::ICC_NEG;
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case SPCC::ICC_NEG: return SPCC::ICC_POS;
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case SPCC::ICC_VC: return SPCC::ICC_VS;
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case SPCC::ICC_VS: return SPCC::ICC_VC;
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case SPCC::FCC_U: return SPCC::FCC_O;
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case SPCC::FCC_O: return SPCC::FCC_U;
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case SPCC::FCC_G: return SPCC::FCC_LE;
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case SPCC::FCC_LE: return SPCC::FCC_G;
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case SPCC::FCC_UG: return SPCC::FCC_ULE;
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case SPCC::FCC_ULE: return SPCC::FCC_UG;
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case SPCC::FCC_L: return SPCC::FCC_GE;
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case SPCC::FCC_GE: return SPCC::FCC_L;
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case SPCC::FCC_UL: return SPCC::FCC_UGE;
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case SPCC::FCC_UGE: return SPCC::FCC_UL;
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case SPCC::FCC_LG: return SPCC::FCC_UE;
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case SPCC::FCC_UE: return SPCC::FCC_LG;
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case SPCC::FCC_NE: return SPCC::FCC_E;
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case SPCC::FCC_E: return SPCC::FCC_NE;
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}
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llvm_unreachable("Invalid cond code");
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}
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MachineInstr *
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SparcInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
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int FrameIx,
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uint64_t Offset,
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const MDNode *MDPtr,
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DebugLoc dl) const {
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MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
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.addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
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return &*MIB;
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}
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bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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MachineBasicBlock::iterator UnCondBrIter = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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//When we see a non-terminator, we are done
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if (!isUnpredicatedTerminator(I))
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break;
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//Terminator is not a branch
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if (!I->isBranch())
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return true;
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//Handle Unconditional branches
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if (I->getOpcode() == SP::BA) {
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UnCondBrIter = I;
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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while (llvm::next(I) != MBB.end())
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llvm::next(I)->eraseFromParent();
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Cond.clear();
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FBB = 0;
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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UnCondBrIter = MBB.end();
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continue;
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}
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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unsigned Opcode = I->getOpcode();
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if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
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return true; //Unknown Opcode
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SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
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if (Cond.empty()) {
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MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
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if (AllowModify && UnCondBrIter != MBB.end() &&
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MBB.isLayoutSuccessor(TargetBB)) {
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//Transform the code
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//
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// brCC L1
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// ba L2
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// L1:
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// ..
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// L2:
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//
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// into
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//
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// brnCC L2
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// L1:
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// ...
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// L2:
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//
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BranchCode = GetOppositeBranchCondition(BranchCode);
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MachineBasicBlock::iterator OldInst = I;
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
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.addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
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BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
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.addMBB(TargetBB);
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OldInst->eraseFromParent();
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UnCondBrIter->eraseFromParent();
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UnCondBrIter = MBB.end();
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I = MBB.end();
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continue;
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}
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FBB = TBB;
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TBB = I->getOperand(0).getMBB();
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Cond.push_back(MachineOperand::CreateImm(BranchCode));
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continue;
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}
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//FIXME: Handle subsequent conditional branches
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//For now, we can't handle multiple conditional branches
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return true;
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}
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return false;
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}
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unsigned
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SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const {
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"Sparc branch conditions should have one component!");
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if (Cond.empty()) {
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
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return 1;
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}
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//Conditional branch
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unsigned CC = Cond[0].getImm();
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if (IsIntegerCC(CC))
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BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
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else
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BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
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if (!FBB)
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return 1;
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BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
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return 2;
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}
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unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (I->getOpcode() != SP::BA
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&& I->getOpcode() != SP::BCOND
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&& I->getOpcode() != SP::FBCOND)
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break; // Not a branch
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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void SparcInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == &SP::IntRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else if (RC == &SP::FPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else if (RC == &SP::DFPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
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.addReg(SrcReg, getKillRegState(isKill));
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else
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llvm_unreachable("Can't store this register to stack slot");
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}
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void SparcInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == &SP::IntRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == &SP::FPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == &SP::DFPRegsRegClass)
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BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
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else
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llvm_unreachable("Can't load this register from stack slot");
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}
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unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
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{
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SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
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unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
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if (GlobalBaseReg != 0)
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return GlobalBaseReg;
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// Insert the set of GlobalBaseReg into the first MBB of the function
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MachineBasicBlock &FirstMBB = MF->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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MachineRegisterInfo &RegInfo = MF->getRegInfo();
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GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
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DebugLoc dl;
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BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
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SparcFI->setGlobalBaseReg(GlobalBaseReg);
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return GlobalBaseReg;
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}
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