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This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
203 lines
7.4 KiB
C++
203 lines
7.4 KiB
C++
//==-- AArch64MCInstLower.cpp - Convert AArch64 MachineInstr to an MCInst --==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower AArch64 MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64MCInstLower.h"
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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AArch64MCInstLower::AArch64MCInstLower(MCContext &ctx, Mangler &mang,
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AsmPrinter &printer)
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: Ctx(ctx), Printer(printer), TargetTriple(printer.getTargetTriple()) {}
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MCSymbol *
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AArch64MCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
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return Printer.getSymbol(MO.getGlobal());
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}
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MCSymbol *
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AArch64MCInstLower::GetExternalSymbolSymbol(const MachineOperand &MO) const {
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return Printer.GetExternalSymbolSymbol(MO.getSymbolName());
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}
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MCOperand AArch64MCInstLower::lowerSymbolOperandDarwin(const MachineOperand &MO,
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MCSymbol *Sym) const {
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// FIXME: We would like an efficient form for this, so we don't have to do a
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// lot of extra uniquing.
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MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
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if ((MO.getTargetFlags() & AArch64II::MO_GOT) != 0) {
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if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_PAGE)
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RefKind = MCSymbolRefExpr::VK_GOTPAGE;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) ==
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AArch64II::MO_PAGEOFF)
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RefKind = MCSymbolRefExpr::VK_GOTPAGEOFF;
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else
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assert(0 && "Unexpected target flags with MO_GOT on GV operand");
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} else if ((MO.getTargetFlags() & AArch64II::MO_TLS) != 0) {
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if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_PAGE)
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RefKind = MCSymbolRefExpr::VK_TLVPPAGE;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) ==
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AArch64II::MO_PAGEOFF)
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RefKind = MCSymbolRefExpr::VK_TLVPPAGEOFF;
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else
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llvm_unreachable("Unexpected target flags with MO_TLS on GV operand");
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} else {
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if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_PAGE)
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RefKind = MCSymbolRefExpr::VK_PAGE;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) ==
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AArch64II::MO_PAGEOFF)
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RefKind = MCSymbolRefExpr::VK_PAGEOFF;
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}
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const MCExpr *Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
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if (!MO.isJTI() && MO.getOffset())
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Expr = MCBinaryExpr::CreateAdd(
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Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), Ctx);
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return MCOperand::CreateExpr(Expr);
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}
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MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
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MCSymbol *Sym) const {
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uint32_t RefFlags = 0;
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if (MO.getTargetFlags() & AArch64II::MO_GOT)
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RefFlags |= AArch64MCExpr::VK_GOT;
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else if (MO.getTargetFlags() & AArch64II::MO_TLS) {
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TLSModel::Model Model;
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if (MO.isGlobal()) {
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const GlobalValue *GV = MO.getGlobal();
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Model = Printer.TM.getTLSModel(GV);
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} else {
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assert(MO.isSymbol() &&
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StringRef(MO.getSymbolName()) == "_TLS_MODULE_BASE_" &&
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"unexpected external TLS symbol");
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Model = TLSModel::GeneralDynamic;
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}
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switch (Model) {
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case TLSModel::InitialExec:
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RefFlags |= AArch64MCExpr::VK_GOTTPREL;
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break;
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case TLSModel::LocalExec:
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RefFlags |= AArch64MCExpr::VK_TPREL;
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break;
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case TLSModel::LocalDynamic:
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RefFlags |= AArch64MCExpr::VK_DTPREL;
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break;
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case TLSModel::GeneralDynamic:
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RefFlags |= AArch64MCExpr::VK_TLSDESC;
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break;
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}
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} else {
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// No modifier means this is a generic reference, classified as absolute for
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// the cases where it matters (:abs_g0: etc).
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RefFlags |= AArch64MCExpr::VK_ABS;
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}
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if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_PAGE)
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RefFlags |= AArch64MCExpr::VK_PAGE;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) ==
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AArch64II::MO_PAGEOFF)
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RefFlags |= AArch64MCExpr::VK_PAGEOFF;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_G3)
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RefFlags |= AArch64MCExpr::VK_G3;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_G2)
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RefFlags |= AArch64MCExpr::VK_G2;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_G1)
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RefFlags |= AArch64MCExpr::VK_G1;
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else if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_G0)
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RefFlags |= AArch64MCExpr::VK_G0;
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if (MO.getTargetFlags() & AArch64II::MO_NC)
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RefFlags |= AArch64MCExpr::VK_NC;
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const MCExpr *Expr =
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MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, Ctx);
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if (!MO.isJTI() && MO.getOffset())
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Expr = MCBinaryExpr::CreateAdd(
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Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), Ctx);
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AArch64MCExpr::VariantKind RefKind;
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RefKind = static_cast<AArch64MCExpr::VariantKind>(RefFlags);
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Expr = AArch64MCExpr::Create(Expr, RefKind, Ctx);
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return MCOperand::CreateExpr(Expr);
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}
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MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
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MCSymbol *Sym) const {
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if (TargetTriple.isOSDarwin())
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return lowerSymbolOperandDarwin(MO, Sym);
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assert(TargetTriple.isOSBinFormatELF() && "Expect Darwin or ELF target");
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return lowerSymbolOperandELF(MO, Sym);
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}
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bool AArch64MCInstLower::lowerOperand(const MachineOperand &MO,
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MCOperand &MCOp) const {
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switch (MO.getType()) {
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default:
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assert(0 && "unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return false;
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MCOp = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_RegisterMask:
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// Regmasks are like implicit defs.
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return false;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = MCOperand::CreateExpr(
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MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(), Ctx));
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = LowerSymbolOperand(MO, GetGlobalAddressSymbol(MO));
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = LowerSymbolOperand(MO, GetExternalSymbolSymbol(MO));
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = LowerSymbolOperand(MO, Printer.GetJTISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = LowerSymbolOperand(MO, Printer.GetCPISymbol(MO.getIndex()));
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = LowerSymbolOperand(
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MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()));
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break;
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}
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return true;
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}
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void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MCOperand MCOp;
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if (lowerOperand(MI->getOperand(i), MCOp))
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OutMI.addOperand(MCOp);
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}
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}
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