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c9de9e60b9
v2[fi]64 values need to be explicitly passed in VSX registers. This is because the code in TRI that finds the minimal register class given a register and a value type will assert if given an Altivec register and a non-Altivec type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205041 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
785 B
LLVM
27 lines
785 B
LLVM
; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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declare <2 x double> @sv(<2 x double>, <2 x i64>, <4 x float>) #0
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define <2 x double> @main(<4 x float> %a, <2 x double> %b, <2 x i64> %c) #1 {
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entry:
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%ca = tail call <2 x double> @sv(<2 x double> %b, <2 x i64> %c, <4 x float> %a)
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%v = fadd <2 x double> %ca, <double 1.0, double 1.0>
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ret <2 x double> %v
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; CHECK-LABEL: @main
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; CHECK-DAG: vor [[V:[0-9]+]], 2, 2
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; CHECK-DAG: xxlor 34, 35, 35
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; CHECK-DAG: xxlor 35, 36, 36
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; CHECK-DAG: vor 4, [[V]], [[V]]
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; CHECK-DAG: bl sv
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; CHECK-DAG: lxvd2x [[VC:[0-9]+]],
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; CHECK: xvadddp 34, 34, [[VC]]
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; CHECK: blr
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}
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attributes #0 = { noinline nounwind readnone }
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attributes #1 = { nounwind }
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