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https://github.com/c64scene-ar/llvm-6502.git
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b9803a8fa6
load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
116 lines
3.6 KiB
C++
116 lines
3.6 KiB
C++
//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expand pseudo instructions into target
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// instructions to allow proper scheduling, if-conversion, and other late
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// optimizations. This pass should be run after register allocation but before
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// post- regalloc scheduling pass.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-pseudo"
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#include "ARM.h"
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#include "ARMBaseInstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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namespace {
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class ARMExpandPseudo : public MachineFunctionPass {
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public:
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static char ID;
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ARMExpandPseudo() : MachineFunctionPass(&ID) {}
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const TargetInstrInfo *TII;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "ARM pseudo instruction expansion pass";
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}
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private:
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bool ExpandMBB(MachineBasicBlock &MBB);
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};
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char ARMExpandPseudo::ID = 0;
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}
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bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineInstr &MI = *MBBI;
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MachineBasicBlock::iterator NMBBI = next(MBBI);
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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default: break;
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case ARM::tLDRpci_pic:
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case ARM::t2LDRpci_pic: {
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unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
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? ARM::tLDRpci : ARM::t2LDRpci;
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unsigned DstReg = MI.getOperand(0).getReg();
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if (!MI.getOperand(0).isDead()) {
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MachineInstr *NewMI =
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(NewLdOpc), DstReg)
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.addOperand(MI.getOperand(1)));
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NewMI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
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.addReg(DstReg, getDefRegState(true))
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.addReg(DstReg)
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.addOperand(MI.getOperand(2));
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}
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MI.eraseFromParent();
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Modified = true;
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break;
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}
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case ARM::t2MOVi32imm: {
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned Imm = MI.getOperand(1).getImm();
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unsigned Lo16 = Imm & 0xffff;
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unsigned Hi16 = (Imm >> 16) & 0xffff;
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if (!MI.getOperand(0).isDead()) {
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(ARM::t2MOVi16), DstReg)
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.addImm(Lo16));
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AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(ARM::t2MOVTi16))
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.addReg(DstReg, getDefRegState(true))
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.addReg(DstReg).addImm(Hi16));
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}
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MI.eraseFromParent();
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Modified = true;
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}
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// FIXME: expand t2MOVi32imm
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}
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getTarget().getInstrInfo();
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bool Modified = false;
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for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
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++MFI)
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Modified |= ExpandMBB(*MFI);
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return Modified;
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}
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/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
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/// expansion pass.
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FunctionPass *llvm::createARMExpandPseudoPass() {
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return new ARMExpandPseudo();
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}
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