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e8eafdb676
This intrinsic is lowered into equivalent copy_s.w instructions during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191518 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.6 KiB
Plaintext
40 lines
1.6 KiB
Plaintext
Code Generation Notes for MSA
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=============================
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Intrinsics are lowered to SelectionDAG nodes where possible in order to enable
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optimisation, reduce the size of the ISel matcher, and reduce repetition in
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the implementation. In a small number of cases, this can cause different
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(semantically equivalent) instructions to be used in place of the requested
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instruction, even when no optimisation has taken place.
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Instructions
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============
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This section describes any quirks of instruction selection for MSA. For
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example, two instructions might be equally valid for some given IR and one is
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chosen in preference to the other.
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vshf.w:
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It is not possible to emit vshf.w when the shuffle description is
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constant since shf.w covers exactly the same cases. shf.w is used
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instead. It is also impossible for the shuffle description to be
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unknown at compile-time due to the definition of shufflevector in
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LLVM IR.
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ilvl.d, pckev.d:
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It is not possible to emit ilvl.d, or pckev.d since ilvev.d covers the
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same shuffle. ilvev.d will be emitted instead.
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ilvr.d, ilvod.d, pckod.d:
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It is not possible to emit ilvr.d, or pckod.d since ilvod.d covers the
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same shuffle. ilvod.d will be emitted instead.
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splati.w:
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It is not possible to emit splati.w since shf.w covers the same cases.
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shf.w will be emitted instead.
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copy_s.w
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On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
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copy_u.w. This is semantically equivalent since the general-purpose
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register file is 32-bits wide.
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