Quentin Colombet ad3c6289b6 [AArch64] Run a peephole pass right after AdvSIMD pass. ... The AdvSIMD pass may produce copies that are not coalescer-friendly. The peephole optimizer knows how to fix that as demonstrated in the test case. <rdar://problem/12702965> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216200 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-21 18:10:07 +00:00
..
AArch64	[AArch64] Run a peephole pass right after AdvSIMD pass.	2014-08-21 18:10:07 +00:00
ARM	Add a thread-model knob for lowering atomics on baremetal & single threaded systems	2014-08-21 14:35:47 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Fix fmul combines with constant splat vectors	2014-08-16 10:14:19 +00:00
MSP430
NVPTX
PowerPC	Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).	2014-08-19 19:05:24 +00:00
R600	R600/SI: Move all fabs / fneg handling to patterns	2014-08-15 18:42:22 +00:00
SPARC
SystemZ
Thumb	Thumb1 load/store optimizer: Improve code to materialize new base register.	2014-08-21 17:11:03 +00:00
Thumb2	[ARM] Enable DP copy, load and store instructions for FPv4-SP	2014-08-21 12:50:31 +00:00
X86	DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments.	2014-08-21 13:28:02 +00:00
XCore