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https://github.com/c64scene-ar/llvm-6502.git
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a7321a6e53
Add handling for FK_SecRel_4 (4-byte section relative relocations). These are used by the generation of DWARF debug information (the abbrevations use section relative relocations). This will also be used in generation of CodeView line tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207941 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.6 KiB
C++
77 lines
2.6 KiB
C++
//===-- ARMWinCOFFObjectWriter.cpp - ARM Windows COFF Object Writer -- C++ -==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/ARMFixupKinds.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/MC/MCWinCOFFObjectWriter.h"
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#include "llvm/Support/COFF.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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namespace {
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class ARMWinCOFFObjectWriter : public MCWinCOFFObjectTargetWriter {
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public:
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ARMWinCOFFObjectWriter(bool Is64Bit)
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: MCWinCOFFObjectTargetWriter(COFF::IMAGE_FILE_MACHINE_ARMNT) {
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assert(!Is64Bit && "AArch64 support not yet implemented");
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}
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virtual ~ARMWinCOFFObjectWriter() { }
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unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup,
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bool IsCrossSection) const override;
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};
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unsigned ARMWinCOFFObjectWriter::getRelocType(const MCValue &Target,
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const MCFixup &Fixup,
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bool IsCrossSection) const {
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assert(getMachine() == COFF::IMAGE_FILE_MACHINE_ARMNT &&
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"AArch64 support not yet implemented");
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MCSymbolRefExpr::VariantKind Modifier =
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Target.isAbsolute() ? MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
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switch (static_cast<unsigned>(Fixup.getKind())) {
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default: llvm_unreachable("unsupported relocation type");
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case FK_Data_4:
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switch (Modifier) {
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case MCSymbolRefExpr::VK_COFF_IMGREL32:
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return COFF::IMAGE_REL_ARM_ADDR32NB;
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case MCSymbolRefExpr::VK_SECREL:
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return COFF::IMAGE_REL_ARM_SECREL;
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default:
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return COFF::IMAGE_REL_ARM_ADDR32;
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}
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case FK_SecRel_4:
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return COFF::IMAGE_REL_ARM_SECREL;
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case ARM::fixup_t2_condbranch:
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return COFF::IMAGE_REL_ARM_BRANCH20T;
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case ARM::fixup_t2_uncondbranch:
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return COFF::IMAGE_REL_ARM_BRANCH24T;
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case ARM::fixup_arm_thumb_bl:
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case ARM::fixup_arm_thumb_blx:
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return COFF::IMAGE_REL_ARM_BLX23T;
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case ARM::fixup_t2_movw_lo16:
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return COFF::IMAGE_REL_ARM_MOV32T;
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case ARM::fixup_t2_movt_hi16:
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llvm_unreachable("High-word for pair-wise relocations are contiguously "
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"addressed as an IMAGE_REL_ARM_MOV32T relocation");
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}
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}
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}
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namespace llvm {
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MCObjectWriter *createARMWinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit) {
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MCWinCOFFObjectTargetWriter *MOTW = new ARMWinCOFFObjectWriter(Is64Bit);
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return createWinCOFFObjectWriter(MOTW, OS);
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}
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}
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