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These objects are internal to the TargetMachine object and may change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183485 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.3 KiB
C++
72 lines
2.3 KiB
C++
//==- AArch64RegisterInfo.h - AArch64 Register Information Impl -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the MCRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_AARCH64REGISTERINFO_H
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#define LLVM_TARGET_AARCH64REGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "AArch64GenRegisterInfo.inc"
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namespace llvm {
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class AArch64InstrInfo;
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class AArch64Subtarget;
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struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
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AArch64RegisterInfo();
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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const uint32_t *getTLSDescCallPreservedMask() const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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unsigned getFrameRegister(const MachineFunction &MF) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *Rs = NULL) const;
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns original class if it is
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/// possible to copy between a two registers of the specified class.
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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/// getLargestLegalSuperClass - Returns the largest super class of RC that is
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/// legal to use in the current sub-target and has the same spill size.
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const TargetRegisterClass*
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getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
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if (RC == &AArch64::tcGPR64RegClass)
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return &AArch64::GPR64RegClass;
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return RC;
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}
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bool requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool useFPForScavengingIndex(const MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif // LLVM_TARGET_AARCH64REGISTERINFO_H
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