Juergen Ributzka 40017084f7 [FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved. ... Sign-/zero-extend folding depended on the load and the integer extend to be both selected by FastISel. This cannot always be garantueed and SelectionDAG might interfer. This commit adds additonal checks to load and integer extend lowering to catch this. Related to rdar://problem/18495928. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219716 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-14 20:36:02 +00:00
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AArch64	[FastISel][AArch64] Fix sign-/zero-extend folding when SelectionDAG is involved.	2014-10-14 20:36:02 +00:00
ARM	Adds support for the Cortex-A17 to the ARM backend	2014-10-13 10:22:19 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Mark redundant instructions with a comment in test/CodeGen/Mips/Fast-ISel/icmpa.ll.	2014-10-13 10:18:02 +00:00
MSP430
NVPTX
PowerPC	Improve sqrt estimate algorithm (fast-math)	2014-10-09 21:26:35 +00:00
R600	Reapply "R600: Add new intrinsic to read work dimensions"	2014-10-14 20:05:26 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	Fix a broadcast related regression on the vector shuffle lowering.	2014-10-13 16:16:16 +00:00
XCore