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Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
896 lines
32 KiB
C++
896 lines
32 KiB
C++
//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of a target
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// register file for a code generator. It uses instances of the Register,
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// RegisterAliases, and RegisterClass classes to gather this information.
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//
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//===----------------------------------------------------------------------===//
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#include "RegisterInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "CodeGenRegisters.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/Format.h"
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#include <algorithm>
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#include <set>
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using namespace llvm;
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// runEnums - Print out enum values for all of the registers.
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void
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RegisterInfoEmitter::runEnums(raw_ostream &OS,
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CodeGenTarget &Target, CodeGenRegBank &Bank) {
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const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
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std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
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EmitSourceFileHeader("Target Register Enum Values", OS);
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OS << "\n#ifdef GET_REGINFO_ENUM\n";
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OS << "#undef GET_REGINFO_ENUM\n";
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OS << "namespace llvm {\n\n";
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OS << "class MCRegisterClass;\n"
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<< "extern const MCRegisterClass " << Namespace
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<< "MCRegisterClasses[];\n\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoRegister,\n";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i)
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OS << " " << Registers[i]->getName() << " = " <<
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Registers[i]->EnumValue << ",\n";
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assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
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"Register enum value mismatch!");
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OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
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OS << "};\n";
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if (!Namespace.empty())
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OS << "}\n";
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ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
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if (!RegisterClasses.empty()) {
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OS << "\n// Register classes\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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if (i) OS << ",\n";
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OS << " " << RegisterClasses[i]->getName() << "RegClassID";
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OS << " = " << i;
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}
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OS << "\n };\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
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// If the only definition is the default NoRegAltName, we don't need to
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// emit anything.
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if (RegAltNameIndices.size() > 1) {
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OS << "\n// Register alternate name indices\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n";
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for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
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OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
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OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
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OS << "};\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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OS << "} // End llvm namespace \n";
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OS << "#endif // GET_REGINFO_ENUM\n\n";
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}
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void
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RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
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const std::vector<CodeGenRegister*> &Regs,
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bool isCtor) {
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// Collect all information about dwarf register numbers
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typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
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DwarfRegNumsMapTy DwarfRegNums;
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// First, just pull all provided information to the map
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unsigned maxLength = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *Reg = Regs[i]->TheDef;
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std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
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maxLength = std::max((size_t)maxLength, RegNums.size());
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if (DwarfRegNums.count(Reg))
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errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
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<< "specified multiple times\n";
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DwarfRegNums[Reg] = RegNums;
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}
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if (!maxLength)
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return;
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// Now we know maximal length of number list. Append -1's, where needed
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
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for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
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I->second.push_back(-1);
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// Emit reverse information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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OS << " switch (";
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if (j == 0)
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OS << "DwarfFlavour";
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else
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OS << "EHFlavour";
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OS << ") {\n"
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<< " default:\n"
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<< " assert(0 && \"Unknown DWARF flavour\");\n"
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<< " break;\n";
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << " case " << i << ":\n";
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
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int DwarfRegNo = I->second[i];
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if (DwarfRegNo < 0)
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continue;
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OS << " ";
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if (!isCtor)
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OS << "RI->";
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OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
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<< getQualifiedName(I->first) << ", ";
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if (j == 0)
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OS << "false";
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else
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OS << "true";
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OS << " );\n";
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}
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OS << " break;\n";
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}
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OS << " }\n";
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}
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *Reg = Regs[i]->TheDef;
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const RecordVal *V = Reg->getValue("DwarfAlias");
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if (!V || !V->getValue())
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continue;
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DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
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Record *Alias = DI->getDef();
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DwarfRegNums[Reg] = DwarfRegNums[Alias];
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}
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// Emit information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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OS << " switch (";
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if (j == 0)
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OS << "DwarfFlavour";
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else
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OS << "EHFlavour";
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OS << ") {\n"
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<< " default:\n"
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<< " assert(0 && \"Unknown DWARF flavour\");\n"
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<< " break;\n";
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << " case " << i << ":\n";
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// Sort by name to get a stable order.
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
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int RegNo = I->second[i];
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OS << " ";
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if (!isCtor)
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OS << "RI->";
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OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
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<< RegNo << ", ";
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if (j == 0)
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OS << "false";
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else
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OS << "true";
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OS << " );\n";
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}
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OS << " break;\n";
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}
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OS << " }\n";
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}
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}
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// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
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// Width is the number of bits per hex number.
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static void printBitVectorAsHex(raw_ostream &OS,
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const BitVector &Bits,
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unsigned Width) {
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assert(Width <= 32 && "Width too large");
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unsigned Digits = (Width + 3) / 4;
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for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
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unsigned Value = 0;
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for (unsigned j = 0; j != Width && i + j != e; ++j)
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Value |= Bits.test(i + j) << j;
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OS << format("0x%0*x, ", Digits, Value);
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}
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}
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// Helper to emit a set of bits into a constant byte array.
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class BitVectorEmitter {
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BitVector Values;
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public:
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void add(unsigned v) {
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if (v >= Values.size())
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Values.resize(((v/8)+1)*8); // Round up to the next byte.
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Values[v] = true;
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}
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void print(raw_ostream &OS) {
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printBitVectorAsHex(OS, Values, 8);
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}
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};
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//
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// runMCDesc - Print out MC register descriptions.
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//
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void
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RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
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CodeGenRegBank &RegBank) {
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EmitSourceFileHeader("MC Register Information", OS);
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OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
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OS << "#undef GET_REGINFO_MC_DESC\n";
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std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
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RegBank.computeOverlaps(Overlaps);
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OS << "namespace llvm {\n\n";
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const std::string &TargetName = Target.getName();
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OS << "\nnamespace {\n";
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const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
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// Emit an overlap list for all registers.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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const CodeGenRegister *Reg = Regs[i];
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const CodeGenRegister::Set &O = Overlaps[Reg];
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// Move Reg to the front so TRI::getAliasSet can share the list.
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OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
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<< getQualifiedName(Reg->TheDef) << ", ";
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for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
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I != E; ++I)
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if (*I != Reg)
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OS << getQualifiedName((*I)->TheDef) << ", ";
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OS << "0 };\n";
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}
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// Emit the empty sub-registers list
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OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
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// Loop over all of the registers which have sub-registers, emitting the
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// sub-registers list to memory.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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const CodeGenRegister &Reg = *Regs[i];
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if (Reg.getSubRegs().empty())
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continue;
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// getSubRegs() orders by SubRegIndex. We want a topological order.
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SetVector<CodeGenRegister*> SR;
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Reg.addSubRegsPreOrder(SR);
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OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
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for (unsigned j = 0, je = SR.size(); j != je; ++j)
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OS << getQualifiedName(SR[j]->TheDef) << ", ";
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OS << "0 };\n";
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}
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// Emit the empty super-registers list
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OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
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// Loop over all of the registers which have super-registers, emitting the
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// super-registers list to memory.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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const CodeGenRegister &Reg = *Regs[i];
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const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
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if (SR.empty())
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continue;
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OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
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for (unsigned j = 0, je = SR.size(); j != je; ++j)
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OS << getQualifiedName(SR[j]->TheDef) << ", ";
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OS << "0 };\n";
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}
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OS << "}\n"; // End of anonymous namespace...
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OS << "\nextern const MCRegisterDesc " << TargetName
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<< "RegDesc[] = { // Descriptors\n";
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OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
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// Now that register alias and sub-registers sets have been emitted, emit the
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// register descriptors now.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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const CodeGenRegister &Reg = *Regs[i];
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OS << " { \"";
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OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
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if (!Reg.getSubRegs().empty())
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OS << Reg.getName() << "_SubRegsSet,\t";
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else
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OS << "Empty_SubRegsSet,\t";
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if (!Reg.getSuperRegs().empty())
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OS << Reg.getName() << "_SuperRegsSet";
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else
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OS << "Empty_SuperRegsSet";
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OS << " },\n";
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}
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OS << "};\n\n"; // End of register descriptors...
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ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
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// Loop over all of the register classes... emitting each one.
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OS << "namespace { // Register classes...\n";
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// Emit the register enum value arrays for each RegisterClass
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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ArrayRef<Record*> Order = RC.getOrder();
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.getName();
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// Emit the register list now.
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OS << " // " << Name << " Register Class...\n"
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<< " static const unsigned " << Name
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<< "[] = {\n ";
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for (unsigned i = 0, e = Order.size(); i != e; ++i) {
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Record *Reg = Order[i];
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OS << getQualifiedName(Reg) << ", ";
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}
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OS << "\n };\n\n";
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OS << " // " << Name << " Bit set.\n"
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<< " static const unsigned char " << Name
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<< "Bits[] = {\n ";
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BitVectorEmitter BVE;
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for (unsigned i = 0, e = Order.size(); i != e; ++i) {
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Record *Reg = Order[i];
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BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
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}
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BVE.print(OS);
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OS << "\n };\n\n";
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}
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OS << "}\n\n";
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OS << "extern const MCRegisterClass " << TargetName
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<< "MCRegisterClasses[] = {\n";
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
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<< '\"' << RC.getName() << "\", "
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<< RC.SpillSize/8 << ", "
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<< RC.SpillAlignment/8 << ", "
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<< RC.CopyCost << ", "
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<< RC.Allocatable << ", "
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<< RC.getName() << ", " << RC.getName() << " + "
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<< RC.getOrder().size() << ", "
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<< RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
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<< "),\n";
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}
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OS << "};\n\n";
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// MCRegisterInfo initialization routine.
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OS << "static inline void Init" << TargetName
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<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
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<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
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OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
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<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
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<< RegisterClasses.size() << ");\n\n";
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EmitRegMapping(OS, Regs, false);
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OS << "}\n\n";
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OS << "} // End llvm namespace \n";
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OS << "#endif // GET_REGINFO_MC_DESC\n\n";
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}
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void
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RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
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CodeGenRegBank &RegBank) {
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EmitSourceFileHeader("Register Information Header Fragment", OS);
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OS << "\n#ifdef GET_REGINFO_HEADER\n";
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OS << "#undef GET_REGINFO_HEADER\n";
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const std::string &TargetName = Target.getName();
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std::string ClassName = TargetName + "GenRegisterInfo";
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OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
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OS << "#include <string>\n\n";
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OS << "namespace llvm {\n\n";
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OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
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<< " explicit " << ClassName
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<< "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
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<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
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<< " { return false; }\n"
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<< " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
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<< " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
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<< " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
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<< " const TargetRegisterClass *"
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"getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
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<< " const TargetRegisterClass *getMatchingSuperRegClass("
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"const TargetRegisterClass*, const TargetRegisterClass*, "
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"unsigned) const;\n"
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<< "};\n\n";
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const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
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if (!SubRegIndices.empty()) {
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OS << "\n// Subregister indices\n";
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std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoSubRegister,\n";
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for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
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OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
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OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
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OS << "};\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0]->Namespace
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<< " { // Register classes\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = *RegisterClasses[i];
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const std::string &Name = RC.getName();
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// Output the register class definition.
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OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
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<< " " << Name << "Class();\n";
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|
if (!RC.AltOrderSelect.empty())
|
|
OS << " ArrayRef<unsigned> "
|
|
"getRawAllocationOrder(const MachineFunction&) const;\n";
|
|
OS << " };\n";
|
|
|
|
// Output the extern for the instance.
|
|
OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
|
|
// Output the extern for the pointer to the instance (should remove).
|
|
OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
|
|
<< Name << "RegClass;\n";
|
|
}
|
|
OS << "} // end of namespace " << TargetName << "\n\n";
|
|
}
|
|
OS << "} // End llvm namespace \n";
|
|
OS << "#endif // GET_REGINFO_HEADER\n\n";
|
|
}
|
|
|
|
//
|
|
// runTargetDesc - Output the target register and register file descriptions.
|
|
//
|
|
void
|
|
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|
CodeGenRegBank &RegBank){
|
|
EmitSourceFileHeader("Target Register and Register Classes Information", OS);
|
|
|
|
OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
|
|
OS << "#undef GET_REGINFO_TARGET_DESC\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
// Get access to MCRegisterClass data.
|
|
OS << "extern const MCRegisterClass " << Target.getName()
|
|
<< "MCRegisterClasses[];\n";
|
|
|
|
// Start out by emitting each of the register classes.
|
|
ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
|
|
|
|
// Collect all registers belonging to any allocatable class.
|
|
std::set<Record*> AllocatableRegs;
|
|
|
|
// Collect allocatable registers.
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
ArrayRef<Record*> Order = RC.getOrder();
|
|
|
|
if (RC.Allocatable)
|
|
AllocatableRegs.insert(Order.begin(), Order.end());
|
|
}
|
|
|
|
OS << "namespace { // Register classes...\n";
|
|
|
|
// Emit the ValueType arrays for each RegisterClass
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
|
|
// Give the register class a legal C name if it's anonymous.
|
|
std::string Name = RC.getName() + "VTs";
|
|
|
|
// Emit the register list now.
|
|
OS << " // " << Name
|
|
<< " Register Class Value Types...\n"
|
|
<< " static const EVT " << Name
|
|
<< "[] = {\n ";
|
|
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
|
|
OS << getEnumName(RC.VTs[i]) << ", ";
|
|
OS << "MVT::Other\n };\n\n";
|
|
}
|
|
OS << "} // end anonymous namespace\n\n";
|
|
|
|
// Now that all of the structs have been emitted, emit the instances.
|
|
if (!RegisterClasses.empty()) {
|
|
OS << "namespace " << RegisterClasses[0]->Namespace
|
|
<< " { // Register class instances\n";
|
|
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
|
|
OS << " " << RegisterClasses[i]->getName() << "Class\t"
|
|
<< RegisterClasses[i]->getName() << "RegClass;\n";
|
|
|
|
std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
|
|
|
|
OS << "\n static const TargetRegisterClass* const "
|
|
<< "NullRegClasses[] = { NULL };\n\n";
|
|
|
|
unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
|
|
|
|
if (NumSubRegIndices) {
|
|
// Compute the super-register classes for each RegisterClass
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
for (DenseMap<Record*,Record*>::const_iterator
|
|
i = RC.SubRegClasses.begin(),
|
|
e = RC.SubRegClasses.end(); i != e; ++i) {
|
|
// Find the register class number of i->second for SuperRegClassMap.
|
|
const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
|
|
assert(RC2 && "Invalid register class in SubRegClasses");
|
|
SuperRegClassMap[RC2->EnumValue].insert(rc);
|
|
}
|
|
}
|
|
|
|
// Emit the super-register classes for each RegisterClass
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
|
|
// Give the register class a legal C name if it's anonymous.
|
|
std::string Name = RC.getName();
|
|
|
|
OS << " // " << Name
|
|
<< " Super-register Classes...\n"
|
|
<< " static const TargetRegisterClass* const "
|
|
<< Name << "SuperRegClasses[] = {\n ";
|
|
|
|
bool Empty = true;
|
|
std::map<unsigned, std::set<unsigned> >::iterator I =
|
|
SuperRegClassMap.find(rc);
|
|
if (I != SuperRegClassMap.end()) {
|
|
for (std::set<unsigned>::iterator II = I->second.begin(),
|
|
EE = I->second.end(); II != EE; ++II) {
|
|
const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
|
|
if (!Empty)
|
|
OS << ", ";
|
|
OS << "&" << RC2.getQualifiedName() << "RegClass";
|
|
Empty = false;
|
|
}
|
|
}
|
|
|
|
OS << (!Empty ? ", " : "") << "NULL";
|
|
OS << "\n };\n\n";
|
|
}
|
|
}
|
|
|
|
// Emit the sub-classes array for each RegisterClass
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
|
|
// Give the register class a legal C name if it's anonymous.
|
|
std::string Name = RC.getName();
|
|
|
|
OS << " static const unsigned " << Name << "SubclassMask[] = { ";
|
|
printBitVectorAsHex(OS, RC.getSubClasses(), 32);
|
|
OS << "};\n\n";
|
|
}
|
|
|
|
// Emit NULL terminated super-class lists.
|
|
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
|
|
ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
|
|
|
|
// Skip classes without supers. We can reuse NullRegClasses.
|
|
if (Supers.empty())
|
|
continue;
|
|
|
|
OS << " static const TargetRegisterClass* const "
|
|
<< RC.getName() << "Superclasses[] = {\n";
|
|
for (unsigned i = 0; i != Supers.size(); ++i)
|
|
OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
|
|
OS << " NULL\n };\n\n";
|
|
}
|
|
|
|
// Emit methods.
|
|
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[i];
|
|
OS << RC.getName() << "Class::" << RC.getName()
|
|
<< "Class() : TargetRegisterClass(&"
|
|
<< Target.getName() << "MCRegisterClasses["
|
|
<< RC.getName() + "RegClassID" << "], "
|
|
<< RC.getName() + "VTs" << ", "
|
|
<< RC.getName() + "SubclassMask" << ", ";
|
|
if (RC.getSuperClasses().empty())
|
|
OS << "NullRegClasses, ";
|
|
else
|
|
OS << RC.getName() + "Superclasses, ";
|
|
OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
|
|
<< "RegClasses"
|
|
<< ") {}\n";
|
|
if (!RC.AltOrderSelect.empty()) {
|
|
OS << "\nstatic inline unsigned " << RC.getName()
|
|
<< "AltOrderSelect(const MachineFunction &MF) {"
|
|
<< RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
|
|
<< RC.getName() << "Class::"
|
|
<< "getRawAllocationOrder(const MachineFunction &MF) const {\n";
|
|
for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
|
|
ArrayRef<Record*> Elems = RC.getOrder(oi);
|
|
OS << " static const unsigned AltOrder" << oi << "[] = {";
|
|
for (unsigned elem = 0; elem != Elems.size(); ++elem)
|
|
OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
|
|
OS << " };\n";
|
|
}
|
|
OS << " const MCRegisterClass &MCR = " << Target.getName()
|
|
<< "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];"
|
|
<< " static const ArrayRef<unsigned> Order[] = {\n"
|
|
<< " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
|
|
for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
|
|
OS << "),\n makeArrayRef(AltOrder" << oi;
|
|
OS << ")\n };\n const unsigned Select = " << RC.getName()
|
|
<< "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
|
|
<< ");\n return Order[Select];\n}\n";
|
|
}
|
|
}
|
|
|
|
OS << "}\n";
|
|
}
|
|
|
|
OS << "\nnamespace {\n";
|
|
OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
|
|
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
|
|
OS << " &" << RegisterClasses[i]->getQualifiedName()
|
|
<< "RegClass,\n";
|
|
OS << " };\n";
|
|
OS << "}\n"; // End of anonymous namespace...
|
|
|
|
// Emit extra information about registers.
|
|
const std::string &TargetName = Target.getName();
|
|
OS << "\n static const TargetRegisterInfoDesc "
|
|
<< TargetName << "RegInfoDesc[] = "
|
|
<< "{ // Extra Descriptors\n";
|
|
OS << " { 0, 0 },\n";
|
|
|
|
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister &Reg = *Regs[i];
|
|
OS << " { ";
|
|
OS << Reg.CostPerUse << ", "
|
|
<< int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
|
|
}
|
|
OS << " };\n"; // End of register descriptors...
|
|
|
|
|
|
// Calculate the mapping of subregister+index pairs to physical registers.
|
|
// This will also create further anonymous indexes.
|
|
unsigned NamedIndices = RegBank.getNumNamedIndices();
|
|
|
|
// Emit SubRegIndex names, skipping 0
|
|
const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
|
|
OS << "\n static const char *const " << TargetName
|
|
<< "SubRegIndexTable[] = { \"";
|
|
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
|
|
OS << SubRegIndices[i]->getName();
|
|
if (i+1 != e)
|
|
OS << "\", \"";
|
|
}
|
|
OS << "\" };\n\n";
|
|
|
|
// Emit names of the anonymus subreg indexes.
|
|
if (SubRegIndices.size() > NamedIndices) {
|
|
OS << " enum {";
|
|
for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
|
|
OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
|
|
if (i+1 != e)
|
|
OS << ',';
|
|
}
|
|
OS << "\n };\n\n";
|
|
}
|
|
OS << "\n";
|
|
|
|
std::string ClassName = Target.getName() + "GenRegisterInfo";
|
|
|
|
// Emit the subregister + index mapping function based on the information
|
|
// calculated above.
|
|
OS << "unsigned " << ClassName
|
|
<< "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
|
|
<< " switch (RegNo) {\n"
|
|
<< " default:\n return 0;\n";
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
|
|
if (SRM.empty())
|
|
continue;
|
|
OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
|
|
OS << " switch (Index) {\n";
|
|
OS << " default: return 0;\n";
|
|
for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
|
|
ie = SRM.end(); ii != ie; ++ii)
|
|
OS << " case " << getQualifiedName(ii->first)
|
|
<< ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
|
|
OS << " };\n" << " break;\n";
|
|
}
|
|
OS << " };\n";
|
|
OS << " return 0;\n";
|
|
OS << "}\n\n";
|
|
|
|
OS << "unsigned " << ClassName
|
|
<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
|
|
<< " switch (RegNo) {\n"
|
|
<< " default:\n return 0;\n";
|
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
|
const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
|
|
if (SRM.empty())
|
|
continue;
|
|
OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
|
|
for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
|
|
ie = SRM.end(); ii != ie; ++ii)
|
|
OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
|
|
<< ") return " << getQualifiedName(ii->first) << ";\n";
|
|
OS << " return 0;\n";
|
|
}
|
|
OS << " };\n";
|
|
OS << " return 0;\n";
|
|
OS << "}\n\n";
|
|
|
|
// Emit composeSubRegIndices
|
|
OS << "unsigned " << ClassName
|
|
<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
|
|
<< " switch (IdxA) {\n"
|
|
<< " default:\n return IdxB;\n";
|
|
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
|
|
bool Open = false;
|
|
for (unsigned j = 0; j != e; ++j) {
|
|
if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
|
|
SubRegIndices[j])) {
|
|
if (!Open) {
|
|
OS << " case " << getQualifiedName(SubRegIndices[i])
|
|
<< ": switch(IdxB) {\n default: return IdxB;\n";
|
|
Open = true;
|
|
}
|
|
OS << " case " << getQualifiedName(SubRegIndices[j])
|
|
<< ": return " << getQualifiedName(Comp) << ";\n";
|
|
}
|
|
}
|
|
if (Open)
|
|
OS << " }\n";
|
|
}
|
|
OS << " }\n}\n\n";
|
|
|
|
// Emit getSubClassWithSubReg.
|
|
OS << "const TargetRegisterClass *" << ClassName
|
|
<< "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
|
|
" const {\n";
|
|
if (SubRegIndices.empty()) {
|
|
OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
|
|
<< " return RC;\n";
|
|
} else {
|
|
// Use the smallest type that can hold a regclass ID with room for a
|
|
// sentinel.
|
|
if (RegisterClasses.size() < UINT8_MAX)
|
|
OS << " static const uint8_t Table[";
|
|
else if (RegisterClasses.size() < UINT16_MAX)
|
|
OS << " static const uint16_t Table[";
|
|
else
|
|
throw "Too many register classes.";
|
|
OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
|
|
for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rci];
|
|
OS << " {\t// " << RC.getName() << "\n";
|
|
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
|
Record *Idx = SubRegIndices[sri];
|
|
if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
|
|
OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
|
|
<< " -> " << SRC->getName() << "\n";
|
|
else
|
|
OS << " 0,\t// " << Idx->getName() << "\n";
|
|
}
|
|
OS << " },\n";
|
|
}
|
|
OS << " };\n assert(RC && \"Missing regclass\");\n"
|
|
<< " if (!Idx) return RC;\n --Idx;\n"
|
|
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
|
|
<< " unsigned TV = Table[RC->getID()][Idx];\n"
|
|
<< " return TV ? getRegClass(TV - 1) : 0;\n";
|
|
}
|
|
OS << "}\n\n";
|
|
|
|
// Emit getMatchingSuperRegClass.
|
|
OS << "const TargetRegisterClass *" << ClassName
|
|
<< "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
|
|
" const TargetRegisterClass *B, unsigned Idx) const {\n";
|
|
if (SubRegIndices.empty()) {
|
|
OS << " llvm_unreachable(\"Target has no sub-registers\");\n";
|
|
} else {
|
|
// We need to find the largest sub-class of A such that every register has
|
|
// an Idx sub-register in B. Map (B, Idx) to a bit-vector of
|
|
// super-register classes that map into B. Then compute the largest common
|
|
// sub-class with A by taking advantage of the register class ordering,
|
|
// like getCommonSubClass().
|
|
|
|
// Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
|
|
// the number of 32-bit words required to represent all register classes.
|
|
const unsigned BVWords = (RegisterClasses.size()+31)/32;
|
|
BitVector BV(RegisterClasses.size());
|
|
|
|
OS << " static const unsigned Table[" << RegisterClasses.size()
|
|
<< "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
|
|
for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
|
|
const CodeGenRegisterClass &RC = *RegisterClasses[rci];
|
|
OS << " {\t// " << RC.getName() << "\n";
|
|
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
|
Record *Idx = SubRegIndices[sri];
|
|
BV.reset();
|
|
RC.getSuperRegClasses(Idx, BV);
|
|
OS << " { ";
|
|
printBitVectorAsHex(OS, BV, 32);
|
|
OS << "},\t// " << Idx->getName() << '\n';
|
|
}
|
|
OS << " },\n";
|
|
}
|
|
OS << " };\n assert(A && B && \"Missing regclass\");\n"
|
|
<< " --Idx;\n"
|
|
<< " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
|
|
<< " const unsigned *TV = Table[B->getID()][Idx];\n"
|
|
<< " const unsigned *SC = A->getSubClassMask();\n"
|
|
<< " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
|
|
<< " if (unsigned Common = TV[i] & SC[i])\n"
|
|
<< " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
|
|
<< " return 0;\n";
|
|
}
|
|
OS << "}\n\n";
|
|
|
|
// Emit the constructor of the class...
|
|
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
|
|
|
|
OS << ClassName << "::" << ClassName
|
|
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
|
|
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
|
|
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
|
|
<< " " << TargetName << "SubRegIndexTable) {\n"
|
|
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
|
<< Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
|
|
<< RegisterClasses.size() << ");\n\n";
|
|
|
|
EmitRegMapping(OS, Regs, true);
|
|
|
|
OS << "}\n\n";
|
|
|
|
OS << "} // End llvm namespace \n";
|
|
OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
|
|
}
|
|
|
|
void RegisterInfoEmitter::run(raw_ostream &OS) {
|
|
CodeGenTarget Target(Records);
|
|
CodeGenRegBank &RegBank = Target.getRegBank();
|
|
RegBank.computeDerivedInfo();
|
|
|
|
runEnums(OS, Target, RegBank);
|
|
runMCDesc(OS, Target, RegBank);
|
|
runTargetHeader(OS, Target, RegBank);
|
|
runTargetDesc(OS, Target, RegBank);
|
|
}
|