Misha Brukman 406d9abc9e All store instructions really want 'rd' in the first field. ...

Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and
expect %fsr as the parameter in assembly. They are disabled (since not used)
until an encoding, both for code generation and output, is chosen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6619 91177308-0d34-0410-b5e6-96231b3b80d8

2003-06-05 01:06:10 +00:00

..

Analysis

Be more robust in the face of undefined behavior.

2003-06-02 05:42:39 +00:00

Archive

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AsmParser

Fix bugs:

2003-05-21 17:48:56 +00:00

Bytecode

Fix bug: Assembler/2003-05-03-BytecodeReaderProblem.llx

2003-05-22 18:35:38 +00:00

CodeGen

I have finally seen the light. The code to change the opcode must live higher in

2003-06-04 04:54:06 +00:00

ExecutionEngine

* Institute a hack for the Sparc call to mmap() to get our generated code to be

2003-06-04 19:45:25 +00:00

Linker

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Support

Make _sure_ we don't go into an infinite loop if a signal happens!

2003-05-27 16:25:04 +00:00

Target

All store instructions really want 'rd' in the first field.

2003-06-05 01:06:10 +00:00

Transforms

Make this work with counter > 127

2003-06-04 20:08:47 +00:00

VMCore

* Make assertion message useful

2003-06-02 17:42:47 +00:00

Makefile

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