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https://github.com/c64scene-ar/llvm-6502.git
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97b5beb7fe
define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147827 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
2.7 KiB
LLVM
102 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=x86_64-apple-macosx < %s | FileCheck %s
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; rdar://7610418
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%ptr = type { i8* }
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%struct.s1 = type { %ptr, %ptr }
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%struct.s2 = type { i32, i8*, i8*, [256 x %struct.s1*], [8 x i32], i64, i8*, i32, i64, i64, i32, %struct.s3*, %struct.s3*, [49 x i64] }
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%struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 }
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define fastcc i8* @t(i32 %base) nounwind {
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entry:
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; CHECK: t:
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; CHECK: leaq (%rax,%rax,4)
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%0 = zext i32 %base to i64
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%1 = getelementptr inbounds %struct.s2* null, i64 %0
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br i1 undef, label %bb1, label %bb2
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bb1:
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; CHECK: %bb1
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; CHECK-NOT: shlq $9
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; CHECK-NOT: leaq
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; CHECK: call
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%2 = getelementptr inbounds %struct.s2* null, i64 %0, i32 0
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call void @bar(i32* %2) nounwind
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unreachable
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bb2:
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; CHECK: %bb2
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; CHECK-NOT: leaq
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; CHECK: callq
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%3 = call fastcc i8* @foo(%struct.s2* %1) nounwind
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unreachable
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bb3:
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ret i8* undef
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}
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declare void @bar(i32*)
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declare fastcc i8* @foo(%struct.s2*) nounwind
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; rdar://8773371
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declare void @printf(...) nounwind
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define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
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; CHECK: commute:
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entry:
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switch i32 %test_case, label %sw.bb307 [
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i32 1, label %sw.bb
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i32 2, label %sw.bb
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i32 3, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry, %entry
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%mul = mul nsw i32 %test_case, 3
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%mul20 = mul nsw i32 %mul, %scale
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br i1 undef, label %if.end34, label %sw.bb307
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if.end34: ; preds = %sw.bb
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; CHECK: %if.end34
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; CHECK: imull
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; CHECK: leal
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; CHECK-NOT: imull
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tail call void (...)* @printf(i32 %test_case, i32 %mul20) nounwind
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%tmp = mul i32 %scale, %test_case
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%tmp752 = mul i32 %tmp, 3
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%tmp753 = zext i32 %tmp752 to i64
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br label %bb.nph743.us
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for.body53.us: ; preds = %bb.nph743.us, %for.body53.us
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%exitcond = icmp eq i64 undef, %tmp753
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br i1 %exitcond, label %bb.nph743.us, label %for.body53.us
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bb.nph743.us: ; preds = %for.body53.us, %if.end34
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br label %for.body53.us
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sw.bb307: ; preds = %sw.bb, %entry
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ret void
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}
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; CSE physical register defining instruction across MBB boundary.
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; rdar://10660865
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define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: cross_mbb_phys_cse:
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; CHECK: cmpl
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; CHECK: ja
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%cmp = icmp ugt i32 %a, %b
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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; CHECK-NOT: cmpl
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; CHECK: sbbl
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%cmp1 = icmp ult i32 %a, %b
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%. = sext i1 %cmp1 to i32
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br label %return
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return: ; preds = %if.end, %entry
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%retval.0 = phi i32 [ 1, %entry ], [ %., %if.end ]
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ret i32 %retval.0
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}
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