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https://github.com/c64scene-ar/llvm-6502.git
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72062f5744
This patch adds support for AArch64 (ARM's 64-bit architecture) to
LLVM in the "experimental" category. Currently, it won't be built
unless requested explicitly.
This initial commit should have support for:
+ Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions
(except the late addition CRC instructions).
+ CodeGen features required for C++03 and C99.
+ Compilation for the "small" memory model: code+static data <
4GB.
+ Absolute and position-independent code.
+ GNU-style (i.e. "__thread") TLS.
+ Debugging information.
The principal omission, currently, is performance tuning.
This patch excludes the NEON support also reviewed due to an outbreak of
batshit insanity in our legal department. That will be committed soon bringing
the changes to precisely what has been approved.
Further reviews would be gratefully received.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
2.0 KiB
C++
77 lines
2.0 KiB
C++
//===-- ARMMCExpr.h - ARM specific MC expression classes --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMMCEXPR_H
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#define ARMMCEXPR_H
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#include "llvm/MC/MCExpr.h"
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namespace llvm {
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class ARMMCExpr : public MCTargetExpr {
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public:
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enum VariantKind {
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VK_ARM_None,
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VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file)
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VK_ARM_LO16 // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .s file)
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};
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private:
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const VariantKind Kind;
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const MCExpr *Expr;
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explicit ARMMCExpr(VariantKind _Kind, const MCExpr *_Expr)
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: Kind(_Kind), Expr(_Expr) {}
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public:
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/// @name Construction
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/// @{
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static const ARMMCExpr *Create(VariantKind Kind, const MCExpr *Expr,
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MCContext &Ctx);
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static const ARMMCExpr *CreateUpper16(const MCExpr *Expr, MCContext &Ctx) {
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return Create(VK_ARM_HI16, Expr, Ctx);
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}
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static const ARMMCExpr *CreateLower16(const MCExpr *Expr, MCContext &Ctx) {
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return Create(VK_ARM_LO16, Expr, Ctx);
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}
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/// @}
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/// @name Accessors
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/// @{
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/// getOpcode - Get the kind of this expression.
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VariantKind getKind() const { return Kind; }
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/// getSubExpr - Get the child of this expression.
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const MCExpr *getSubExpr() const { return Expr; }
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/// @}
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void PrintImpl(raw_ostream &OS) const;
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bool EvaluateAsRelocatableImpl(MCValue &Res,
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const MCAsmLayout *Layout) const;
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void AddValueSymbols(MCAssembler *) const;
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const MCSection *FindAssociatedSection() const {
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return getSubExpr()->FindAssociatedSection();
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}
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// There are no TLS ARMMCExprs at the moment.
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void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
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static bool classof(const MCExpr *E) {
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return E->getKind() == MCExpr::Target;
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}
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};
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} // end namespace llvm
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#endif
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