mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
4b2698cf19
Fixes two latent bugs:
- There was no fence inserted before expanded seq_cst load (unsound on Power)
- There was only a fence release before seq_cst stores (again unsound, in particular on Power)
It is not even clear if this is correct on ARM swift processors (where release fences are
DMB ishst instead of DMB ish). This behaviour is currently preserved on ARM Swift
as it is not clear whether it is incorrect. I would love to get documentation stating
whether it is correct or not.
These two bugs were not triggered because Power is not (yet) using this pass, and these
behaviours happen to be (mostly?) working on ARM
(although they completely butchered the semantics of the llvm IR).
See:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075821.html
for an example of the problems that can be caused by the second of these bugs.
I couldn't see a way of fixing these in a completely target-independent way without
adding lots of unnecessary fences on ARM, hence the target-dependent parts of this
patch.
This patch implements the new target-dependent parts only for ARM (the default
of not doing anything is enough for AArch64), other architectures will use this
infrastructure in later patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217076 91177308-0d34-0410-b5e6-96231b3b80d8
365 lines
14 KiB
LLVM
365 lines
14 KiB
LLVM
; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-expand %s | FileCheck %s
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define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) {
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; CHECK-LABEL: @test_atomic_xchg_i8
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; CHECK-NOT: dmb
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK-NOT: dmb
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic
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ret i8 %res
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}
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define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) {
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; CHECK-LABEL: @test_atomic_add_i16
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
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; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend
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; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i16 [[OLDVAL]]
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%res = atomicrmw add i16* %ptr, i16 %addend seq_cst
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ret i16 %res
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}
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define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) {
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; CHECK-LABEL: @test_atomic_sub_i32
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; CHECK-NOT: dmb
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr)
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; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i32 [[OLDVAL]]
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%res = atomicrmw sub i32* %ptr, i32 %subend acquire
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ret i32 %res
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}
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define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) {
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; CHECK-LABEL: @test_atomic_and_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK-NOT: dmb
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw and i8* %ptr, i8 %andend release
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ret i8 %res
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}
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define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) {
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; CHECK-LABEL: @test_atomic_nand_i16
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
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; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend
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; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1
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; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i16 [[OLDVAL]]
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%res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst
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ret i16 %res
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}
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define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) {
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; CHECK-LABEL: @test_atomic_or_i64
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
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; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
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; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
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; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
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; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
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; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64
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; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32
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; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]]
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; CHECK: [[NEWVAL:%.*]] = or i64 [[OLDVAL]], %orend
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; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32
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; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32
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; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
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; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i64 [[OLDVAL]]
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%res = atomicrmw or i64* %ptr, i64 %orend seq_cst
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ret i64 %res
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}
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define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) {
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; CHECK-LABEL: @test_atomic_xor_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) {
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; CHECK-LABEL: @test_atomic_max_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw max i8* %ptr, i8 %maxend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) {
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; CHECK-LABEL: @test_atomic_min_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw min i8* %ptr, i8 %minend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) {
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; CHECK-LABEL: @test_atomic_umax_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst
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ret i8 %res
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}
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define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) {
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; CHECK-LABEL: @test_atomic_umin_i8
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
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; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend
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; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend
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; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
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; CHECK: [[END]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: ret i8 [[OLDVAL]]
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%res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst
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ret i8 %res
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}
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define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
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; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8
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; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
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; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
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; CHECK: [[TRY_STORE]]:
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; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* %ptr)
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; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
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; CHECK: [[SUCCESS_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[DONE:.*]]
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; CHECK: [[FAILURE_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[DONE]]
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; CHECK: [[DONE]]:
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; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
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; CHECK: ret i8 [[OLDVAL]]
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%pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst
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%old = extractvalue { i8, i1 } %pairold, 0
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ret i8 %old
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}
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define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) {
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; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* %ptr)
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; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
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; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
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; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
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; CHECK: [[TRY_STORE]]:
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; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* %ptr)
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; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
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; CHECK: [[SUCCESS_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[DONE:.*]]
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; CHECK: [[FAILURE_BB]]:
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; CHECK-NOT: dmb
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; CHECK: br label %[[DONE]]
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; CHECK: [[DONE]]:
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; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
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; CHECK: ret i16 [[OLDVAL]]
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%pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic
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%old = extractvalue { i16, i1 } %pairold, 0
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ret i16 %old
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}
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define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) {
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; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire
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; CHECK-NOT: dmb
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* %ptr)
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; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
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; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
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; CHECK: [[TRY_STORE]]:
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; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* %ptr)
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; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
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; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
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; CHECK: [[SUCCESS_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[DONE:.*]]
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; CHECK: [[FAILURE_BB]]:
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; CHECK: call void @llvm.arm.dmb(i32 11)
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; CHECK: br label %[[DONE]]
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; CHECK: [[DONE]]:
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; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
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; CHECK: ret i32 [[OLDVAL]]
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%pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire
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%old = extractvalue { i32, i1 } %pairold, 0
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ret i32 %old
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}
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define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) {
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; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic
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; CHECK-NOT: dmb
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; CHECK: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
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; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
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; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
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; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
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; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
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|
; CHECK: [[HI64_TMP:%.*]] = zext i32 [[HI]] to i64
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|
; CHECK: [[HI64:%.*]] = shl i64 [[HI64_TMP]], 32
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|
; CHECK: [[OLDVAL:%.*]] = or i64 [[LO64]], [[HI64]]
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|
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i64 [[OLDVAL]], %desired
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|
; CHECK: br i1 [[SHOULD_STORE]], label %[[TRY_STORE:.*]], label %[[FAILURE_BB:.*]]
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|
|
|
; CHECK: [[TRY_STORE]]:
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|
; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32
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|
; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32
|
|
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
|
|
; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
|
|
; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
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|
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
|
|
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
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|
|
|
; CHECK: [[SUCCESS_BB]]:
|
|
; CHECK-NOT: dmb
|
|
; CHECK: br label %[[DONE:.*]]
|
|
|
|
; CHECK: [[FAILURE_BB]]:
|
|
; CHECK-NOT: dmb
|
|
; CHECK: br label %[[DONE]]
|
|
|
|
; CHECK: [[DONE]]:
|
|
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
|
|
; CHECK: ret i64 [[OLDVAL]]
|
|
|
|
%pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic
|
|
%old = extractvalue { i64, i1 } %pairold, 0
|
|
ret i64 %old
|
|
}
|