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4150d83abe
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
584 lines
22 KiB
C++
584 lines
22 KiB
C++
//===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class wraps target description classes used by the various code
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// generation TableGen backends. This makes it easier to access the data and
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// provides a single place that needs to check it for validity. All of these
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// classes throw exceptions on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "CodeGenIntrinsics.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Streams.h"
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#include <algorithm>
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using namespace llvm;
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static cl::opt<unsigned>
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AsmWriterNum("asmwriternum", cl::init(0),
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cl::desc("Make -gen-asm-writer emit assembly writer #N"));
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType llvm::getValueType(Record *Rec) {
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return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
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}
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std::string llvm::getName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "UNKNOWN";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::iAny: return "MVT::iAny";
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case MVT::fAny: return "MVT::fAny";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::ppcf128: return "MVT::ppcf128";
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case MVT::Flag: return "MVT::Flag";
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case MVT::isVoid:return "MVT::isVoid";
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case MVT::v2i8: return "MVT::v2i8";
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case MVT::v4i8: return "MVT::v4i8";
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case MVT::v2i16: return "MVT::v2i16";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v1i64: return "MVT::v1i64";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::v3i32: return "MVT::v3i32";
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case MVT::v3f32: return "MVT::v3f32";
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case MVT::iPTR: return "TLI.getPointerTy()";
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case MVT::iPTRAny: return "TLI.getPointerTy()";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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std::string llvm::getEnumName(MVT::SimpleValueType T) {
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switch (T) {
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case MVT::Other: return "MVT::Other";
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case MVT::i1: return "MVT::i1";
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case MVT::i8: return "MVT::i8";
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case MVT::i16: return "MVT::i16";
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case MVT::i32: return "MVT::i32";
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case MVT::i64: return "MVT::i64";
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case MVT::i128: return "MVT::i128";
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case MVT::iAny: return "MVT::iAny";
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case MVT::fAny: return "MVT::fAny";
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case MVT::f32: return "MVT::f32";
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case MVT::f64: return "MVT::f64";
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case MVT::f80: return "MVT::f80";
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case MVT::f128: return "MVT::f128";
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case MVT::ppcf128: return "MVT::ppcf128";
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case MVT::Flag: return "MVT::Flag";
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case MVT::isVoid:return "MVT::isVoid";
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case MVT::v2i8: return "MVT::v2i8";
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case MVT::v4i8: return "MVT::v4i8";
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case MVT::v2i16: return "MVT::v2i16";
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case MVT::v8i8: return "MVT::v8i8";
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case MVT::v4i16: return "MVT::v4i16";
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case MVT::v2i32: return "MVT::v2i32";
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case MVT::v1i64: return "MVT::v1i64";
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case MVT::v16i8: return "MVT::v16i8";
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case MVT::v8i16: return "MVT::v8i16";
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case MVT::v4i32: return "MVT::v4i32";
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case MVT::v2i64: return "MVT::v2i64";
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case MVT::v2f32: return "MVT::v2f32";
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case MVT::v4f32: return "MVT::v4f32";
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case MVT::v2f64: return "MVT::v2f64";
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case MVT::v3i32: return "MVT::v3i32";
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case MVT::v3f32: return "MVT::v3f32";
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case MVT::iPTR: return "MVT::iPTR";
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case MVT::iPTRAny: return "MVT::iPTRAny";
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default: assert(0 && "ILLEGAL VALUE TYPE!"); return "";
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}
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}
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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///
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std::string llvm::getQualifiedName(const Record *R) {
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std::string Namespace = R->getValueAsString("Namespace");
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if (Namespace.empty()) return R->getName();
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return Namespace + "::" + R->getName();
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}
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/// getTarget - Return the current instance of the Target class.
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///
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CodeGenTarget::CodeGenTarget() {
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std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
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if (Targets.size() == 0)
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throw std::string("ERROR: No 'Target' subclasses defined!");
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if (Targets.size() != 1)
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throw std::string("ERROR: Multiple subclasses of Target defined!");
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TargetRec = Targets[0];
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}
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const std::string &CodeGenTarget::getName() const {
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return TargetRec->getName();
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}
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std::string CodeGenTarget::getInstNamespace() const {
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std::string InstNS;
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for (inst_iterator i = inst_begin(), e = inst_end(); i != e; ++i) {
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InstNS = i->second.Namespace;
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// Make sure not to pick up "TargetInstrInfo" by accidentally getting
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// the namespace off the PHI instruction or something.
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if (InstNS != "TargetInstrInfo")
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break;
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}
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return InstNS;
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}
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Record *CodeGenTarget::getInstructionSet() const {
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return TargetRec->getValueAsDef("InstructionSet");
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}
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *CodeGenTarget::getAsmWriter() const {
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std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
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if (AsmWriterNum >= LI.size())
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throw "Target does not have an AsmWriter #" + utostr(AsmWriterNum) + "!";
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return LI[AsmWriterNum];
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}
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void CodeGenTarget::ReadRegisters() const {
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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if (Regs.empty())
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throw std::string("No 'Register' subclasses defined!");
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Registers.reserve(Regs.size());
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Registers.assign(Regs.begin(), Regs.end());
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}
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CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
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DeclaredSpillSize = R->getValueAsInt("SpillSize");
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DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
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}
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const std::string &CodeGenRegister::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadRegisterClasses() const {
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std::vector<Record*> RegClasses =
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Records.getAllDerivedDefinitions("RegisterClass");
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if (RegClasses.empty())
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throw std::string("No 'RegisterClass' subclasses defined!");
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RegisterClasses.reserve(RegClasses.size());
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RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
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}
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std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
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std::vector<unsigned char> Result;
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RegisterClasses[i];
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for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
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if (R == RC.Elements[ei]) {
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const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
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for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
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Result.push_back(InVTs[i]);
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}
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}
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}
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return Result;
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}
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CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
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// Rename anonymous register classes.
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if (R->getName().size() > 9 && R->getName()[9] == '.') {
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static unsigned AnonCounter = 0;
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R->setName("AnonRegClass_"+utostr(AnonCounter++));
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}
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std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
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for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
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Record *Type = TypeList[i];
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if (!Type->isSubClassOf("ValueType"))
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throw "RegTypes list member '" + Type->getName() +
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"' does not derive from the ValueType class!";
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VTs.push_back(getValueType(Type));
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}
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assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
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std::vector<Record*> RegList = R->getValueAsListOfDefs("MemberList");
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for (unsigned i = 0, e = RegList.size(); i != e; ++i) {
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Record *Reg = RegList[i];
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if (!Reg->isSubClassOf("Register"))
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throw "Register Class member '" + Reg->getName() +
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"' does not derive from the Register class!";
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Elements.push_back(Reg);
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}
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std::vector<Record*> SubRegClassList =
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R->getValueAsListOfDefs("SubRegClassList");
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for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
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Record *SubRegClass = SubRegClassList[i];
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if (!SubRegClass->isSubClassOf("RegisterClass"))
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throw "Register Class member '" + SubRegClass->getName() +
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"' does not derive from the RegisterClass class!";
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SubRegClasses.push_back(SubRegClass);
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}
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// Allow targets to override the size in bits of the RegisterClass.
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unsigned Size = R->getValueAsInt("Size");
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Namespace = R->getValueAsString("Namespace");
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SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
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SpillAlignment = R->getValueAsInt("Alignment");
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CopyCost = R->getValueAsInt("CopyCost");
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MethodBodies = R->getValueAsCode("MethodBodies");
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MethodProtos = R->getValueAsCode("MethodProtos");
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}
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const std::string &CodeGenRegisterClass::getName() const {
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return TheDef->getName();
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}
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void CodeGenTarget::ReadLegalValueTypes() const {
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const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
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for (unsigned i = 0, e = RCs.size(); i != e; ++i)
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for (unsigned ri = 0, re = RCs[i].VTs.size(); ri != re; ++ri)
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LegalValueTypes.push_back(RCs[i].VTs[ri]);
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// Remove duplicates.
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std::sort(LegalValueTypes.begin(), LegalValueTypes.end());
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LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
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LegalValueTypes.end()),
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LegalValueTypes.end());
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}
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void CodeGenTarget::ReadInstructions() const {
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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if (Insts.size() <= 2)
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throw std::string("No 'Instruction' subclasses defined!");
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// Parse the instructions defined in the .td file.
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std::string InstFormatName =
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getAsmWriter()->getValueAsString("InstFormatName");
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for (unsigned i = 0, e = Insts.size(); i != e; ++i) {
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std::string AsmStr = Insts[i]->getValueAsString(InstFormatName);
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Instructions.insert(std::make_pair(Insts[i]->getName(),
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CodeGenInstruction(Insts[i], AsmStr)));
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}
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}
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/// getInstructionsByEnumValue - Return all of the instructions defined by the
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/// target, ordered by their enum value.
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void CodeGenTarget::
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getInstructionsByEnumValue(std::vector<const CodeGenInstruction*>
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&NumberedInstructions) {
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std::map<std::string, CodeGenInstruction>::const_iterator I;
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I = getInstructions().find("PHI");
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if (I == Instructions.end()) throw "Could not find 'PHI' instruction!";
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const CodeGenInstruction *PHI = &I->second;
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I = getInstructions().find("INLINEASM");
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if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!";
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const CodeGenInstruction *INLINEASM = &I->second;
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I = getInstructions().find("DBG_LABEL");
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if (I == Instructions.end()) throw "Could not find 'DBG_LABEL' instruction!";
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const CodeGenInstruction *DBG_LABEL = &I->second;
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I = getInstructions().find("EH_LABEL");
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if (I == Instructions.end()) throw "Could not find 'EH_LABEL' instruction!";
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const CodeGenInstruction *EH_LABEL = &I->second;
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I = getInstructions().find("GC_LABEL");
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if (I == Instructions.end()) throw "Could not find 'GC_LABEL' instruction!";
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const CodeGenInstruction *GC_LABEL = &I->second;
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I = getInstructions().find("DECLARE");
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if (I == Instructions.end()) throw "Could not find 'DECLARE' instruction!";
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const CodeGenInstruction *DECLARE = &I->second;
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I = getInstructions().find("EXTRACT_SUBREG");
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if (I == Instructions.end())
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throw "Could not find 'EXTRACT_SUBREG' instruction!";
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const CodeGenInstruction *EXTRACT_SUBREG = &I->second;
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I = getInstructions().find("INSERT_SUBREG");
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if (I == Instructions.end())
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throw "Could not find 'INSERT_SUBREG' instruction!";
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const CodeGenInstruction *INSERT_SUBREG = &I->second;
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I = getInstructions().find("IMPLICIT_DEF");
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if (I == Instructions.end())
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throw "Could not find 'IMPLICIT_DEF' instruction!";
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const CodeGenInstruction *IMPLICIT_DEF = &I->second;
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I = getInstructions().find("SUBREG_TO_REG");
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if (I == Instructions.end())
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throw "Could not find 'SUBREG_TO_REG' instruction!";
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const CodeGenInstruction *SUBREG_TO_REG = &I->second;
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I = getInstructions().find("COPY_TO_REGCLASS");
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if (I == Instructions.end())
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throw "Could not find 'COPY_TO_REGCLASS' instruction!";
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const CodeGenInstruction *COPY_TO_REGCLASS = &I->second;
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// Print out the rest of the instructions now.
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NumberedInstructions.push_back(PHI);
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NumberedInstructions.push_back(INLINEASM);
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NumberedInstructions.push_back(DBG_LABEL);
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NumberedInstructions.push_back(EH_LABEL);
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NumberedInstructions.push_back(GC_LABEL);
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NumberedInstructions.push_back(DECLARE);
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NumberedInstructions.push_back(EXTRACT_SUBREG);
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NumberedInstructions.push_back(INSERT_SUBREG);
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NumberedInstructions.push_back(IMPLICIT_DEF);
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NumberedInstructions.push_back(SUBREG_TO_REG);
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NumberedInstructions.push_back(COPY_TO_REGCLASS);
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for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II)
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if (&II->second != PHI &&
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&II->second != INLINEASM &&
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&II->second != DBG_LABEL &&
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&II->second != EH_LABEL &&
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&II->second != GC_LABEL &&
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&II->second != DECLARE &&
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&II->second != EXTRACT_SUBREG &&
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&II->second != INSERT_SUBREG &&
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&II->second != IMPLICIT_DEF &&
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&II->second != SUBREG_TO_REG &&
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&II->second != COPY_TO_REGCLASS)
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NumberedInstructions.push_back(&II->second);
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}
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/// isLittleEndianEncoding - Return whether this target encodes its instruction
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/// in little-endian format, i.e. bits laid out in the order [0..n]
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///
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bool CodeGenTarget::isLittleEndianEncoding() const {
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return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
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}
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/// supportsHasI1 - Return whether this target supports the implicit I1,
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/// rather than Flags, for ADDC/ADDE
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///
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bool CodeGenTarget::supportsHasI1() const {
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return getInstructionSet()->getValueAsBit("supportsHasI1");
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}
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//===----------------------------------------------------------------------===//
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// ComplexPattern implementation
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//
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ComplexPattern::ComplexPattern(Record *R) {
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Ty = ::getValueType(R->getValueAsDef("Ty"));
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NumOperands = R->getValueAsInt("NumOperands");
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SelectFunc = R->getValueAsString("SelectFunc");
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RootNodes = R->getValueAsListOfDefs("RootNodes");
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// Parse the properties.
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Properties = 0;
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std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
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for (unsigned i = 0, e = PropList.size(); i != e; ++i)
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if (PropList[i]->getName() == "SDNPHasChain") {
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Properties |= 1 << SDNPHasChain;
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} else if (PropList[i]->getName() == "SDNPOptInFlag") {
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Properties |= 1 << SDNPOptInFlag;
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} else if (PropList[i]->getName() == "SDNPMayStore") {
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Properties |= 1 << SDNPMayStore;
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} else if (PropList[i]->getName() == "SDNPMayLoad") {
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Properties |= 1 << SDNPMayLoad;
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} else if (PropList[i]->getName() == "SDNPSideEffect") {
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Properties |= 1 << SDNPSideEffect;
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} else if (PropList[i]->getName() == "SDNPMemOperand") {
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Properties |= 1 << SDNPMemOperand;
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|
} else {
|
|
cerr << "Unsupported SD Node property '" << PropList[i]->getName()
|
|
<< "' on ComplexPattern '" << R->getName() << "'!\n";
|
|
exit(1);
|
|
}
|
|
|
|
// Parse the attributes.
|
|
Attributes = 0;
|
|
PropList = R->getValueAsListOfDefs("Attributes");
|
|
for (unsigned i = 0, e = PropList.size(); i != e; ++i)
|
|
if (PropList[i]->getName() == "CPAttrParentAsRoot") {
|
|
Attributes |= 1 << CPAttrParentAsRoot;
|
|
} else {
|
|
cerr << "Unsupported pattern attribute '" << PropList[i]->getName()
|
|
<< "' on ComplexPattern '" << R->getName() << "'!\n";
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CodeGenIntrinsic Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
|
|
bool TargetOnly) {
|
|
std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
|
|
|
|
std::vector<CodeGenIntrinsic> Result;
|
|
|
|
for (unsigned i = 0, e = I.size(); i != e; ++i) {
|
|
bool isTarget = I[i]->getValueAsBit("isTarget");
|
|
if (isTarget == TargetOnly)
|
|
Result.push_back(CodeGenIntrinsic(I[i]));
|
|
}
|
|
return Result;
|
|
}
|
|
|
|
CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
|
|
TheDef = R;
|
|
std::string DefName = R->getName();
|
|
ModRef = WriteMem;
|
|
isOverloaded = false;
|
|
isCommutative = false;
|
|
|
|
if (DefName.size() <= 4 ||
|
|
std::string(DefName.begin(), DefName.begin() + 4) != "int_")
|
|
throw "Intrinsic '" + DefName + "' does not start with 'int_'!";
|
|
|
|
EnumName = std::string(DefName.begin()+4, DefName.end());
|
|
|
|
if (R->getValue("GCCBuiltinName")) // Ignore a missing GCCBuiltinName field.
|
|
GCCBuiltinName = R->getValueAsString("GCCBuiltinName");
|
|
|
|
TargetPrefix = R->getValueAsString("TargetPrefix");
|
|
Name = R->getValueAsString("LLVMName");
|
|
|
|
if (Name == "") {
|
|
// If an explicit name isn't specified, derive one from the DefName.
|
|
Name = "llvm.";
|
|
|
|
for (unsigned i = 0, e = EnumName.size(); i != e; ++i)
|
|
Name += (EnumName[i] == '_') ? '.' : EnumName[i];
|
|
} else {
|
|
// Verify it starts with "llvm.".
|
|
if (Name.size() <= 5 ||
|
|
std::string(Name.begin(), Name.begin() + 5) != "llvm.")
|
|
throw "Intrinsic '" + DefName + "'s name does not start with 'llvm.'!";
|
|
}
|
|
|
|
// If TargetPrefix is specified, make sure that Name starts with
|
|
// "llvm.<targetprefix>.".
|
|
if (!TargetPrefix.empty()) {
|
|
if (Name.size() < 6+TargetPrefix.size() ||
|
|
std::string(Name.begin() + 5, Name.begin() + 6 + TargetPrefix.size())
|
|
!= (TargetPrefix + "."))
|
|
throw "Intrinsic '" + DefName + "' does not start with 'llvm." +
|
|
TargetPrefix + ".'!";
|
|
}
|
|
|
|
// Parse the list of return types.
|
|
std::vector<MVT::SimpleValueType> OverloadedVTs;
|
|
ListInit *TypeList = R->getValueAsListInit("RetTypes");
|
|
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
|
|
Record *TyEl = TypeList->getElementAsRecord(i);
|
|
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
|
|
MVT::SimpleValueType VT;
|
|
if (TyEl->isSubClassOf("LLVMMatchType")) {
|
|
unsigned MatchTy = TyEl->getValueAsInt("Number");
|
|
assert(MatchTy < OverloadedVTs.size() &&
|
|
"Invalid matching number!");
|
|
VT = OverloadedVTs[MatchTy];
|
|
// It only makes sense to use the extended and truncated vector element
|
|
// variants with iAny types; otherwise, if the intrinsic is not
|
|
// overloaded, all the types can be specified directly.
|
|
assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
|
|
!TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
|
|
VT == MVT::iAny) && "Expected iAny type");
|
|
} else {
|
|
VT = getValueType(TyEl->getValueAsDef("VT"));
|
|
}
|
|
if (VT == MVT::iAny || VT == MVT::fAny || VT == MVT::iPTRAny) {
|
|
OverloadedVTs.push_back(VT);
|
|
isOverloaded |= true;
|
|
}
|
|
IS.RetVTs.push_back(VT);
|
|
IS.RetTypeDefs.push_back(TyEl);
|
|
}
|
|
|
|
if (IS.RetVTs.size() == 0)
|
|
throw "Intrinsic '"+DefName+"' needs at least a type for the ret value!";
|
|
|
|
// Parse the list of parameter types.
|
|
TypeList = R->getValueAsListInit("ParamTypes");
|
|
for (unsigned i = 0, e = TypeList->getSize(); i != e; ++i) {
|
|
Record *TyEl = TypeList->getElementAsRecord(i);
|
|
assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!");
|
|
MVT::SimpleValueType VT;
|
|
if (TyEl->isSubClassOf("LLVMMatchType")) {
|
|
unsigned MatchTy = TyEl->getValueAsInt("Number");
|
|
assert(MatchTy < OverloadedVTs.size() &&
|
|
"Invalid matching number!");
|
|
VT = OverloadedVTs[MatchTy];
|
|
// It only makes sense to use the extended and truncated vector element
|
|
// variants with iAny types; otherwise, if the intrinsic is not
|
|
// overloaded, all the types can be specified directly.
|
|
assert(((!TyEl->isSubClassOf("LLVMExtendedElementVectorType") &&
|
|
!TyEl->isSubClassOf("LLVMTruncatedElementVectorType")) ||
|
|
VT == MVT::iAny) && "Expected iAny type");
|
|
} else
|
|
VT = getValueType(TyEl->getValueAsDef("VT"));
|
|
if (VT == MVT::iAny || VT == MVT::fAny || VT == MVT::iPTRAny) {
|
|
OverloadedVTs.push_back(VT);
|
|
isOverloaded |= true;
|
|
}
|
|
IS.ParamVTs.push_back(VT);
|
|
IS.ParamTypeDefs.push_back(TyEl);
|
|
}
|
|
|
|
// Parse the intrinsic properties.
|
|
ListInit *PropList = R->getValueAsListInit("Properties");
|
|
for (unsigned i = 0, e = PropList->getSize(); i != e; ++i) {
|
|
Record *Property = PropList->getElementAsRecord(i);
|
|
assert(Property->isSubClassOf("IntrinsicProperty") &&
|
|
"Expected a property!");
|
|
|
|
if (Property->getName() == "IntrNoMem")
|
|
ModRef = NoMem;
|
|
else if (Property->getName() == "IntrReadArgMem")
|
|
ModRef = ReadArgMem;
|
|
else if (Property->getName() == "IntrReadMem")
|
|
ModRef = ReadMem;
|
|
else if (Property->getName() == "IntrWriteArgMem")
|
|
ModRef = WriteArgMem;
|
|
else if (Property->getName() == "IntrWriteMem")
|
|
ModRef = WriteMem;
|
|
else if (Property->getName() == "Commutative")
|
|
isCommutative = true;
|
|
else if (Property->isSubClassOf("NoCapture")) {
|
|
unsigned ArgNo = Property->getValueAsInt("ArgNo");
|
|
ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture));
|
|
} else
|
|
assert(0 && "Unknown property!");
|
|
}
|
|
}
|