mirror of
https://github.com/c64scene-ar/llvm-6502.git
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ce665bd2e2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
284 lines
9.9 KiB
C++
284 lines
9.9 KiB
C++
//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the VirtRegMap class.
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//
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// It also contains implementations of the Spiller interface, which, given a
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// virtual register map and a machine function, eliminates all virtual
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// references by replacing them with physical register references - adding spill
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// code as necessary.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "virtregmap"
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#include "VirtRegMap.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumSpills , "Number of register spills");
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//===----------------------------------------------------------------------===//
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// VirtRegMap implementation
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//===----------------------------------------------------------------------===//
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char VirtRegMap::ID = 0;
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INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
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bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
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MRI = &mf.getRegInfo();
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TII = mf.getTarget().getInstrInfo();
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TRI = mf.getTarget().getRegisterInfo();
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MF = &mf;
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ReMatId = MAX_STACK_SLOT+1;
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LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
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Virt2PhysMap.clear();
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Virt2StackSlotMap.clear();
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Virt2ReMatIdMap.clear();
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Virt2SplitMap.clear();
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Virt2SplitKillMap.clear();
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ReMatMap.clear();
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ImplicitDefed.clear();
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SpillSlotToUsesMap.clear();
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MI2VirtMap.clear();
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SpillPt2VirtMap.clear();
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RestorePt2VirtMap.clear();
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EmergencySpillMap.clear();
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EmergencySpillSlots.clear();
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SpillSlotToUsesMap.resize(8);
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ImplicitDefed.resize(MF->getRegInfo().getLastVirtReg()+1-
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TargetRegisterInfo::FirstVirtualRegister);
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allocatableRCRegs.clear();
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for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
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E = TRI->regclass_end(); I != E; ++I)
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allocatableRCRegs.insert(std::make_pair(*I,
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TRI->getAllocatableSet(mf, *I)));
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grow();
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return false;
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}
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void VirtRegMap::grow() {
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unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
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Virt2PhysMap.grow(LastVirtReg);
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Virt2StackSlotMap.grow(LastVirtReg);
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Virt2ReMatIdMap.grow(LastVirtReg);
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Virt2SplitMap.grow(LastVirtReg);
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Virt2SplitKillMap.grow(LastVirtReg);
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ReMatMap.grow(LastVirtReg);
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ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
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}
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unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
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std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
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unsigned physReg = Hint.second;
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if (physReg &&
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TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
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physReg = getPhys(physReg);
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if (Hint.first == 0)
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return (physReg && TargetRegisterInfo::isPhysicalRegister(physReg))
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? physReg : 0;
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return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
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}
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
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int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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RC->getAlignment());
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if (LowSpillSlot == NO_STACK_SLOT)
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LowSpillSlot = SS;
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if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
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HighSpillSlot = SS;
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unsigned Idx = SS-LowSpillSlot;
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while (Idx >= SpillSlotToUsesMap.size())
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SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
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Virt2StackSlotMap[virtReg] = SS;
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++NumSpills;
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return SS;
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}
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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assert((SS >= 0 ||
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(SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
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"illegal fixed frame index");
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Virt2StackSlotMap[virtReg] = SS;
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}
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int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign re-mat id to already spilled register");
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Virt2ReMatIdMap[virtReg] = ReMatId;
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return ReMatId++;
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}
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void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
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assert(TargetRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign re-mat id to already spilled register");
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Virt2ReMatIdMap[virtReg] = id;
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}
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int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
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std::map<const TargetRegisterClass*, int>::iterator I =
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EmergencySpillSlots.find(RC);
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if (I != EmergencySpillSlots.end())
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return I->second;
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int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
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RC->getAlignment());
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if (LowSpillSlot == NO_STACK_SLOT)
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LowSpillSlot = SS;
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if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
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HighSpillSlot = SS;
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EmergencySpillSlots[RC] = SS;
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return SS;
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}
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void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
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if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
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// If FI < LowSpillSlot, this stack reference was produced by
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// instruction selection and is not a spill
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if (FI >= LowSpillSlot) {
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assert(FI >= 0 && "Spill slot index should not be negative!");
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assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
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&& "Invalid spill slot");
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SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
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}
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}
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}
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void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
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MachineInstr *NewMI, ModRef MRInfo) {
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// Move previous memory references folded to new instruction.
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MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
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for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
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E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
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MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
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MI2VirtMap.erase(I++);
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}
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// add new memory reference
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MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
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}
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void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
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MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
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MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
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}
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void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isFI())
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continue;
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int FI = MO.getIndex();
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if (MF->getFrameInfo()->isFixedObjectIndex(FI))
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continue;
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// This stack reference was produced by instruction selection and
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// is not a spill
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if (FI < LowSpillSlot)
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continue;
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assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
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&& "Invalid spill slot");
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SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
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}
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MI2VirtMap.erase(MI);
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SpillPt2VirtMap.erase(MI);
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RestorePt2VirtMap.erase(MI);
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EmergencySpillMap.erase(MI);
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}
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/// FindUnusedRegisters - Gather a list of allocatable registers that
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/// have not been allocated to any virtual register.
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bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
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unsigned NumRegs = TRI->getNumRegs();
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UnusedRegs.reset();
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UnusedRegs.resize(NumRegs);
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BitVector Used(NumRegs);
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for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
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e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
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if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
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Used.set(Virt2PhysMap[i]);
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BitVector Allocatable = TRI->getAllocatableSet(*MF);
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bool AnyUnused = false;
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for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
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if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
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bool ReallyUnused = true;
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
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if (Used[*AS] || LIs->hasInterval(*AS)) {
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ReallyUnused = false;
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break;
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}
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}
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if (ReallyUnused) {
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AnyUnused = true;
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UnusedRegs.set(Reg);
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}
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}
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}
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return AnyUnused;
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}
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void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
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const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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OS << "********** REGISTER MAP **********\n";
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for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
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e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) {
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if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
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OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
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<< "] " << MRI.getRegClass(i)->getName() << "\n";
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}
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for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
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e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
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if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
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OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i]
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<< "] " << MRI.getRegClass(i)->getName() << "\n";
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OS << '\n';
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}
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void VirtRegMap::dump() const {
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print(dbgs());
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}
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