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https://github.com/c64scene-ar/llvm-6502.git
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645efd763d
This should fix the ARM bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197555 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
944 B
LLVM
31 lines
944 B
LLVM
; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon | FileCheck %s
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; CHECK: t1
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; CHECK: vldr d
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; CHECK: vldr d
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; CHECK: vadd.i16 d
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; CHECK: vstr d
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define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
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entry:
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%0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
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%1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
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%2 = add <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
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%3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
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store <2 x i32> %3, <2 x i32>* %r, align 8
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ret void
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}
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; CHECK: t2
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; CHECK: vldr d
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; CHECK: vldr d
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; CHECK: vsub.i16 d
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; CHECK: vmov r0, r1, d
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define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly {
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entry:
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%0 = load <4 x i16>* %a, align 8 ; <<4 x i16>> [#uses=1]
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%1 = load <4 x i16>* %b, align 8 ; <<4 x i16>> [#uses=1]
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%2 = sub <4 x i16> %0, %1 ; <<4 x i16>> [#uses=1]
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%3 = bitcast <4 x i16> %2 to <2 x i32> ; <<2 x i32>> [#uses=1]
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ret <2 x i32> %3
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}
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