llvm-6502/test/CodeGen/ARM64/extload-knownzero.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

29 lines
607 B
LLVM

; RUN: llc < %s -march=arm64 | FileCheck %s
; rdar://12771555
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
; CHECK-LABEL: foo:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
; CHECK: %bb1
; CHECK: ldrh [[REG:w[0-9]+]]
%tmp2 = load i16* %ptr, align 2
br label %bb2
bb2:
; CHECK: %bb2
; CHECK-NOT: and {{w[0-9]+}}, [[REG]], #0xffff
; CHECK: cmp [[REG]], #23
%tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
%cmp = icmp ult i16 %tmp3, 24
br i1 %cmp, label %bb3, label %exit
bb3:
call void @bar() nounwind
br label %exit
exit:
ret void
}
declare void @bar ()