mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
4.2 KiB
LLVM
174 lines
4.2 KiB
LLVM
; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
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; rdar://10263824
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define i1 @fcmp_float1(float %a) nounwind ssp {
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entry:
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; CHECK: @fcmp_float1
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; CHECK: fcmp s0, #0.0
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; CHECK: csinc w0, wzr, wzr, eq
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%cmp = fcmp une float %a, 0.000000e+00
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ret i1 %cmp
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}
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define i1 @fcmp_float2(float %a, float %b) nounwind ssp {
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entry:
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; CHECK: @fcmp_float2
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; CHECK: fcmp s0, s1
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; CHECK: csinc w0, wzr, wzr, eq
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%cmp = fcmp une float %a, %b
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ret i1 %cmp
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}
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define i1 @fcmp_double1(double %a) nounwind ssp {
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entry:
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; CHECK: @fcmp_double1
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; CHECK: fcmp d0, #0.0
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; CHECK: csinc w0, wzr, wzr, eq
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%cmp = fcmp une double %a, 0.000000e+00
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ret i1 %cmp
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}
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define i1 @fcmp_double2(double %a, double %b) nounwind ssp {
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entry:
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; CHECK: @fcmp_double2
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; CHECK: fcmp d0, d1
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; CHECK: csinc w0, wzr, wzr, eq
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%cmp = fcmp une double %a, %b
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ret i1 %cmp
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}
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; Check each fcmp condition
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define float @fcmp_oeq(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_oeq
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne
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%cmp = fcmp oeq float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_ogt(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_ogt
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le
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%cmp = fcmp ogt float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_oge(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_oge
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt
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%cmp = fcmp oge float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_olt(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_olt
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl
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%cmp = fcmp olt float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_ole(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_ole
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi
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%cmp = fcmp ole float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_ord(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_ord
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vs
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%cmp = fcmp ord float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_uno(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_uno
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vc
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%cmp = fcmp uno float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_ugt(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_ugt
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ls
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%cmp = fcmp ugt float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_uge(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_uge
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, mi
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%cmp = fcmp uge float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_ult(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_ult
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ge
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%cmp = fcmp ult float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_ule(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_ule
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt
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%cmp = fcmp ule float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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define float @fcmp_une(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_une
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; CHECK: fcmp s0, s1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
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%cmp = fcmp une float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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; Possible opportunity for improvement. See comment in
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; ARM64TargetLowering::LowerSETCC()
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define float @fcmp_one(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_one
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; fcmp s0, s1
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; orr w0, wzr, #0x1
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; csel w1, w0, wzr, mi
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; csel w0, w0, wzr, gt
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%cmp = fcmp one float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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; Possible opportunity for improvement. See comment in
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; ARM64TargetLowering::LowerSETCC()
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define float @fcmp_ueq(float %a, float %b) nounwind ssp {
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; CHECK: @fcmp_ueq
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; CHECK: fcmp s0, s1
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; orr w0, wzr, #0x1
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; CHECK: csel [[REG1:w[0-9]]], [[REG2:w[0-9]+]], wzr, eq
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; CHECK: csel {{w[0-9]+}}, [[REG2]], [[REG1]], vs
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%cmp = fcmp ueq float %a, %b
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%conv = uitofp i1 %cmp to float
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ret float %conv
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}
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