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Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
192 lines
7.0 KiB
C++
192 lines
7.0 KiB
C++
//===- BlackfinISelDAGToDAG.cpp - A dag to dag inst selector for Blackfin -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the Blackfin target.
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//
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//===----------------------------------------------------------------------===//
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#include "Blackfin.h"
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#include "BlackfinISelLowering.h"
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#include "BlackfinTargetMachine.h"
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#include "BlackfinRegisterInfo.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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/// BlackfinDAGToDAGISel - Blackfin specific code to select blackfin machine
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/// instructions for SelectionDAG operations.
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namespace {
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class BlackfinDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the Blackfin Subtarget around so that we
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/// can make the right decision when generating code for different targets.
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//const BlackfinSubtarget &Subtarget;
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public:
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BlackfinDAGToDAGISel(BlackfinTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel) {}
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "Blackfin DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "BlackfinGenDAGISel.inc"
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private:
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SDNode *Select(SDValue Op);
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bool SelectADDRspii(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Offset);
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// Walk the DAG after instruction selection, fixing register class issues.
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void FixRegisterClasses(SelectionDAG &DAG);
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const BlackfinInstrInfo &getInstrInfo() {
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return *static_cast<const BlackfinTargetMachine&>(TM).getInstrInfo();
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}
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const BlackfinRegisterInfo *getRegisterInfo() {
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return static_cast<const BlackfinTargetMachine&>(TM).getRegisterInfo();
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}
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};
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} // end anonymous namespace
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FunctionPass *llvm::createBlackfinISelDag(BlackfinTargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new BlackfinDAGToDAGISel(TM, OptLevel);
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void BlackfinDAGToDAGISel::InstructionSelect() {
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// Select target instructions for the DAG.
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SelectRoot(*CurDAG);
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DOUT << "Selected selection DAG before regclass fixup:\n";
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DEBUG(CurDAG->dump());
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FixRegisterClasses(*CurDAG);
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}
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SDNode *BlackfinDAGToDAGISel::Select(SDValue Op) {
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SDNode *N = Op.getNode();
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DebugLoc dl = N->getDebugLoc();
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if (N->isMachineOpcode())
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return NULL; // Already selected.
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switch (N->getOpcode()) {
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default: break;
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case ISD::FrameIndex: {
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// Selects to ADDpp FI, 0 which in turn will become ADDimm7 SP, imm or ADDpp
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// SP, Px
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
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return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI,
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CurDAG->getTargetConstant(0, MVT::i32));
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}
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}
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return SelectCode(Op);
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}
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bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Op,
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SDValue Addr,
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SDValue &Base,
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SDValue &Offset) {
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FrameIndexSDNode *FIN = 0;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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ConstantSDNode *CN = 0;
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if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) &&
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(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
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(CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
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// Constant positive word offset from frame index
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
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return true;
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}
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}
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return false;
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}
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static inline bool isCC(const TargetRegisterClass *RC) {
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return RC == &BF::AnyCCRegClass || BF::AnyCCRegClass.hasSubClass(RC);
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}
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static inline bool isDCC(const TargetRegisterClass *RC) {
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return RC == &BF::DRegClass || BF::DRegClass.hasSubClass(RC) || isCC(RC);
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}
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static void UpdateNodeOperand(SelectionDAG &DAG,
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SDNode *N,
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unsigned Num,
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SDValue Val) {
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SmallVector<SDValue, 8> ops(N->op_begin(), N->op_end());
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ops[Num] = Val;
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SDValue New = DAG.UpdateNodeOperands(SDValue(N, 0), ops.data(), ops.size());
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DAG.ReplaceAllUsesWith(N, New.getNode());
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}
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// After instruction selection, insert COPY_TO_REGCLASS nodes to help in
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// choosing the proper register classes.
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void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) {
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const BlackfinInstrInfo &TII = getInstrInfo();
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const BlackfinRegisterInfo *TRI = getRegisterInfo();
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DAG.AssignTopologicalOrder();
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HandleSDNode Dummy(DAG.getRoot());
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for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin();
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NI != DAG.allnodes_end(); ++NI) {
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if (NI->use_empty() || !NI->isMachineOpcode())
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continue;
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const TargetInstrDesc &DefTID = TII.get(NI->getMachineOpcode());
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for (SDNode::use_iterator UI = NI->use_begin(); !UI.atEnd(); ++UI) {
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if (!UI->isMachineOpcode())
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continue;
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if (UI.getUse().getResNo() >= DefTID.getNumDefs())
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continue;
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const TargetRegisterClass *DefRC =
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DefTID.OpInfo[UI.getUse().getResNo()].getRegClass(TRI);
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const TargetInstrDesc &UseTID = TII.get(UI->getMachineOpcode());
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if (UseTID.getNumDefs()+UI.getOperandNo() >= UseTID.getNumOperands())
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continue;
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const TargetRegisterClass *UseRC =
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UseTID.OpInfo[UseTID.getNumDefs()+UI.getOperandNo()].getRegClass(TRI);
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if (!DefRC || !UseRC)
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continue;
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// We cannot copy CC <-> !(CC/D)
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if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) {
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SDNode *Copy =
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DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS,
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NI->getDebugLoc(),
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MVT::i32,
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UI.getUse().get(),
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DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
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UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0));
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}
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}
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}
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DAG.setRoot(Dummy.getValue());
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}
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