Eric Christopher f27805b5c5 Have fast-isel understand llvm.objectsize. Update testcase for slightly ... different codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98244 91177308-0d34-0410-b5e6-96231b3b80d8		2010-03-11 06:20:22 +00:00
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Alpha
ARM	Enable machine cse pass.	2010-03-10 03:07:41 +00:00
Blackfin
CBackend
CellSPU	fix bss section printing for cell, patch by Kalle Raiskila!	2010-03-05 18:55:36 +00:00
CPP
Generic
MBlaze	Re-committing the failed r97807 commit with changes to eliminate warnings.	2010-03-06 23:23:12 +00:00
Mips
MSP430	Do not use '&' prefix for globals when register base field is non-zero, otherwise msp430-as will silently miscompile the code (TI's assembler report an error though).	2010-03-06 11:41:12 +00:00
PIC16
PowerPC	Enable machine cse pass.	2010-03-10 03:07:41 +00:00
SPARC
SystemZ
Thumb	Enable machine cse pass.	2010-03-10 03:07:41 +00:00
Thumb2	Enable machine cse pass.	2010-03-10 03:07:41 +00:00
X86	Have fast-isel understand llvm.objectsize. Update testcase for slightly	2010-03-11 06:20:22 +00:00
XCore	Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit	2010-03-10 18:12:27 +00:00