mirror of
https://github.com/c64scene-ar/llvm-6502.git
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9920f561c3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214929 91177308-0d34-0410-b5e6-96231b3b80d8
114 lines
3.8 KiB
C++
114 lines
3.8 KiB
C++
//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMTARGETMACHINE_H
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#define ARMTARGETMACHINE_H
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#include "ARMInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class ARMBaseTargetMachine : public LLVMTargetMachine {
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protected:
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ARMSubtarget Subtarget;
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public:
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ARMBaseTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL,
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bool isLittle);
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const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
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/// \brief Register ARM analysis passes with a pass manager.
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void addAnalysisPasses(PassManagerBase &PM) override;
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// Pass Pipeline Configuration
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
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};
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/// ARMTargetMachine - ARM target machine.
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///
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class ARMTargetMachine : public ARMBaseTargetMachine {
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virtual void anchor();
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public:
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ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
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};
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/// ARMLETargetMachine - ARM little endian target machine.
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///
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class ARMLETargetMachine : public ARMTargetMachine {
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void anchor() override;
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public:
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ARMLETargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// ARMBETargetMachine - ARM big endian target machine.
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///
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class ARMBETargetMachine : public ARMTargetMachine {
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void anchor() override;
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public:
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ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL);
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};
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/// ThumbTargetMachine - Thumb target machine.
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/// Due to the way architectures are handled, this represents both
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/// Thumb-1 and Thumb-2.
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///
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class ThumbTargetMachine : public ARMBaseTargetMachine {
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virtual void anchor();
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public:
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ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
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};
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/// ThumbLETargetMachine - Thumb little endian target machine.
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///
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class ThumbLETargetMachine : public ThumbTargetMachine {
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void anchor() override;
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public:
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ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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/// ThumbBETargetMachine - Thumb big endian target machine.
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///
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class ThumbBETargetMachine : public ThumbTargetMachine {
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void anchor() override;
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public:
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ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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};
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} // end namespace llvm
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#endif
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