Cameron Zwarich 92efda7e91 Merge information about the number of zero, one, and sign bits of live-out registers ... at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes <rdar://problem/8760114>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8		2011-02-22 00:46:27 +00:00
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Alpha
ARM	PR9139: Specify ARM/Darwin triple for vector-DAGCombine.ll test.	2011-02-14 22:12:50 +00:00
Blackfin
CBackend
CellSPU	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
CPP
Generic	A fix for 9165.	2011-02-12 14:40:33 +00:00
MBlaze	fix visitShift to properly zero extend the shift amount if the provided operand	2011-02-13 09:02:52 +00:00
Mips
MSP430	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
PowerPC
PTX
SPARC	Generate correct Sparc32 ABI compliant code for functions that return a struct.	2011-02-21 03:42:44 +00:00
SystemZ
Thumb
Thumb2
X86	Merge information about the number of zero, one, and sign bits of live-out registers	2011-02-22 00:46:27 +00:00
XCore	Add XCore intrinsics for various instructions on ports.	2011-02-21 18:23:30 +00:00