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https://github.com/c64scene-ar/llvm-6502.git
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6495f63945
- This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
44 lines
1.4 KiB
C++
44 lines
1.4 KiB
C++
//===- Thumb2RegisterInfo.h - Thumb-2 Register Information Impl ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef THUMB2REGISTERINFO_H
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#define THUMB2REGISTERINFO_H
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#include "ARM.h"
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#include "ARMRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMBaseInstrInfo;
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class Type;
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struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
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public:
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Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx, int Val,
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ARMCC::CondCodes Pred = ARMCC::AL,
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unsigned PredReg = 0) const;
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bool requiresRegisterScavenging(const MachineFunction &MF) const;
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};
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}
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#endif // THUMB2REGISTERINFO_H
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