Jyotsna Verma 4210da7253 Hexagon: Add V4 compare instructions. Enable relationship mapping ... for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-05 16:42:24 +00:00
..
Analysis	use GEP::accumulateConstantOffset() to replace custom written code to compute GEP offset	2013-02-03 13:17:11 +00:00
Archive
AsmParser	Use the do-while(0) thing for this #define.	2013-02-05 07:19:31 +00:00
Bitcode	Added LLVM Asm/Bitcode Reader/Writer support for new IR keyword externally_initialized.	2013-02-05 05:57:38 +00:00
CodeGen	Revert r174343, "When the target-independent DAGCombiner inferred a higher alignment for a load,"	2013-02-05 14:44:16 +00:00
DebugInfo
ExecutionEngine	Fix misplaced 'break'.	2013-02-01 18:57:06 +00:00
IR	Add target-dependent versions of addAttribute/removeAttribute to AttrBuilder.	2013-02-05 08:09:32 +00:00
Linker
MC	Link .ARM.exidx with corresponding text section.	2013-02-05 14:18:59 +00:00
Object	[Object][Archive] Improve performance.	2013-02-03 10:48:50 +00:00
Option
Support	More MSan/ASan annotations.	2013-02-04 07:03:24 +00:00
TableGen
Target	Hexagon: Add V4 compare instructions. Enable relationship mapping	2013-02-05 16:42:24 +00:00
Transforms	Loop Vectorizer: Handle pointer stores/loads in getWidestType()	2013-02-05 15:08:02 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile