llvm-6502/test/CodeGen/X86/legalizedag_vec.ll
Scott Michel 4214a5531c Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTOR
instruction. The class also consolidates the code for detecting constant
splats that's shared across PowerPC and the CellSPU backends (and might be
useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for
generating new BUILD_VECTOR nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22 23:36:09 +00:00

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LLVM

; RUN: llvm-as < %s | llc -march=x86 -mattr=sse2 -disable-mmx -o %t -f
; RUN: grep divdi3 %t | grep call | count 2
; Test case for r63760 where we generate a legalization assert that an illegal
; type has been inserted by LegalizeDAG after LegalizeType has run. With sse2,
; v2i64 is a legal type but with mmx disabled, i64 is an illegal type. When
; legalizing the divide in LegalizeDAG, we scalarize the vector divide and make
; two 64 bit divide library calls which introduces i64 nodes that needs to be
; promoted.
define <2 x i64> @test_long_div(<2 x i64> %num, <2 x i64> %div) {
%div.r = sdiv <2 x i64> %num, %div
ret <2 x i64> %div.r
}