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https://github.com/c64scene-ar/llvm-6502.git
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972f5896e4
- Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
289 lines
8.7 KiB
C++
289 lines
8.7 KiB
C++
//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Bruno Cardoso Lopes and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-reg-info"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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//#include "MipsSubtarget.h"
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using namespace llvm;
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// TODO: add subtarget support
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MipsRegisterInfo::MipsRegisterInfo(const TargetInstrInfo &tii)
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: MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
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TII(tii) {}
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void MipsRegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::SW)).addFrameIndex(FI)
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.addImm(0).addReg(SrcReg, false, false, true);
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else
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assert(0 && "Can't store this register to stack slot");
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}
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void MipsRegisterInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
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else
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assert(0 && "Can't load this register from stack slot");
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}
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void MipsRegisterInfo::
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const
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{
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if (RC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, TII.get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
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.addReg(SrcReg);
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else
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assert (0 && "Can't copy this register");
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}
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void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const
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{
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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MachineInstr *MipsRegisterInfo::
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foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const
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{
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MachineInstr *NewMI = NULL;
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switch (MI->getOpcode())
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{
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case Mips::ADDu:
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if ((MI->getOperand(0).isRegister()) &&
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(MI->getOperand(1).isRegister()) &&
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(MI->getOperand(1).getReg() == Mips::ZERO) &&
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(MI->getOperand(2).isRegister()))
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{
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if (OpNum == 0) // COPY -> STORE
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NewMI = BuildMI(TII.get(Mips::SW)).addFrameIndex(FI)
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.addImm(0).addReg(MI->getOperand(2).getReg());
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else // COPY -> LOAD
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NewMI = BuildMI(TII.get(Mips::LW), MI->getOperand(0)
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.getReg()).addImm(0).addFrameIndex(FI);
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}
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break;
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}
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if (NewMI)
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NewMI->copyKillDeadInfo(MI);
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return NewMI;
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}
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/// Mips Callee Saved Registers
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const unsigned* MipsRegisterInfo::
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getCalleeSavedRegs() const
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{
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// Mips calle-save register range is $16-$26(s0-s7)
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static const unsigned CalleeSavedRegs[] = {
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Mips::S0, Mips::S1, Mips::S2, Mips::S3,
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Mips::S4, Mips::S5, Mips::S6, Mips::S7, 0
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};
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return CalleeSavedRegs;
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}
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/// Mips Callee Saved Register Classes
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const TargetRegisterClass* const*
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MipsRegisterInfo::getCalleeSavedRegClasses() const
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{
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
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&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, 0
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};
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return CalleeSavedRegClasses;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const
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{
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BitVector Reserved(getNumRegs());
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Reserved.set(Mips::ZERO);
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Reserved.set(Mips::AT);
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Reserved.set(Mips::K0);
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Reserved.set(Mips::K1);
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Reserved.set(Mips::GP);
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Reserved.set(Mips::SP);
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Reserved.set(Mips::FP);
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Reserved.set(Mips::RA);
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// True if target has frame pointer
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bool MipsRegisterInfo::
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hasFP(const MachineFunction &MF) const {
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return false;
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void MipsRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const
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{
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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// FrameInfo addressable stack objects are accessed
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// using neg. offsets, so we must add with the stack
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// size to obtain $sp relative address.
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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int stackSize = MF.getFrameInfo()->getStackSize();
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int spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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#ifndef NDEBUG
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DOUT << "\n<--------->\n";
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MI.print(DOUT);
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DOUT << "FrameIndex : " << FrameIndex << "\n";
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DOUT << "spOffset : " << spOffset << "\n";
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DOUT << "stackSize : " << stackSize << "\n";
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#endif
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// If the FrameIndex points to a positive SPOffset this
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// means we are inside the callee and getting the arguments
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// from the caller stack
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int Offset = (-(stackSize)) + spOffset;
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#ifndef NDEBUG
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DOUT << "Offset : " << Offset << "\n";
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DOUT << "<--------->\n";
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#endif
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MI.getOperand(i-1).ChangeToImmediate(Offset);
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MI.getOperand(i).ChangeToRegister(Mips::SP,false);
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}
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void MipsRegisterInfo::
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emitPrologue(MachineFunction &MF) const
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{
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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// Do we need to allocate space on the stack?
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if (NumBytes == 0) return;
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// FIXME: is Stack Align needed here ?? (maybe it's done before...)
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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NumBytes = -((NumBytes+Align-1)/Align*Align);
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack : addi sp, sp, (-imm)
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BuildMI(MBB, MBB.begin(), TII.get(Mips::ADDi), Mips::SP)
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.addReg(Mips::SP).addImm(NumBytes);
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}
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void MipsRegisterInfo::
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emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
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{
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the number of bytes from FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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// adjust stack : insert addi sp, sp, (imm)
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if (NumBytes) {
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BuildMI(MBB, MBBI, TII.get(Mips::ADDi), Mips::SP)
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.addReg(Mips::SP).addImm(-NumBytes);
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}
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}
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void MipsRegisterInfo::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
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unsigned MipsRegisterInfo::
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getRARegister() const {
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return Mips::RA;
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}
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unsigned MipsRegisterInfo::
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getFrameRegister(MachineFunction &MF) const {
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assert(0 && "What is the frame register");
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return Mips::FP;
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}
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unsigned MipsRegisterInfo::
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getEHExceptionRegister() const {
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assert(0 && "What is the exception register");
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return 0;
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}
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unsigned MipsRegisterInfo::
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getEHHandlerRegister() const {
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assert(0 && "What is the exception handler register");
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return 0;
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}
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#include "MipsGenRegisterInfo.inc"
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