Evan Cheng 5e6b4605bd Rename TargetRegisterDesc to MCRegisterDesc ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8

2011-06-24 23:44:48 +00:00

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bugpoint

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buildit

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count

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crosstool

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emacs

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FileUpdate

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fpcmp

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git

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jedit

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kate

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KillTheDoctor

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lint

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lit

lit support for REQUIRES: asserts.

2011-06-22 23:23:19 +00:00

llvm-lit

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Misc

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not

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PerfectShuffle

In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.

2011-05-18 06:42:21 +00:00

release

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TableGen

Rename TargetRegisterDesc to MCRegisterDesc

2011-06-24 23:44:48 +00:00

Target/ARM

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unittest

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valgrind

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vim

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cgiplotNLT.pl

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check-each-file

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codegen-diff

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countloc.sh

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DSAclean.py

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DSAextract.py

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findmisopt

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findoptdiff

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findsym.pl

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GenLibDeps.pl

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GetRepositoryPath

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GetSourceVersion

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getsrcs.sh

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importNLT.pl

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llvm-native-gcc

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llvm-native-gxx

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llvm.grm

Add a new function attribute, nonlazybind, which inhibits lazy-loading

2011-06-15 20:36:13 +00:00

llvmbuild

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llvmdo

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llvmgrep

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Makefile

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makellvm

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NewNightlyTest.pl

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NightlyTest.gnuplot

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NightlyTestTemplate.html

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NLT.schema

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parseNLT.pl

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plotNLT.pl

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profile.pl

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show-diagnostics

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test_debuginfo.pl

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UpdateCMakeLists.pl

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webNLT.pl

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