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https://github.com/c64scene-ar/llvm-6502.git
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fef8e383eb
If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
662 B
LLVM
24 lines
662 B
LLVM
; RUN: llc -mtriple=arm64-darwin-unknown < %s | FileCheck %s
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%T = type { i32, i32, i32, i32 }
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; Test if the constant base address gets only materialized once.
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define i32 @test1() nounwind {
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; CHECK-LABEL: test1
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; CHECK: movz w8, #1039, lsl #16
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; CHECK-NEXT: movk w8, #49152
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; CHECK-NEXT: ldp w9, w10, [x8, #4]
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; CHECK: ldr w8, [x8, #12]
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%at = inttoptr i64 68141056 to %T*
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%o1 = getelementptr %T* %at, i32 0, i32 1
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%t1 = load i32* %o1
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%o2 = getelementptr %T* %at, i32 0, i32 2
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%t2 = load i32* %o2
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%a1 = add i32 %t1, %t2
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%o3 = getelementptr %T* %at, i32 0, i32 3
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%t3 = load i32* %o3
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%a2 = add i32 %a1, %t3
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ret i32 %a2
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}
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