llvm-6502/test/CodeGen/ARM64/fast-isel-noconvert.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

36 lines
921 B
LLVM

; RUN: llc -mtriple=arm64-apple-ios -O0 %s -o - | FileCheck %s
; Fast-isel can't do vector conversions yet, but it was emitting some highly
; suspect UCVTFUWDri MachineInstrs.
define <4 x float> @test_uitofp(<4 x i32> %in) {
; CHECK-LABEL: test_uitofp:
; CHECK: ucvtf.4s v0, v0
%res = uitofp <4 x i32> %in to <4 x float>
ret <4 x float> %res
}
define <2 x double> @test_sitofp(<2 x i32> %in) {
; CHECK-LABEL: test_sitofp:
; CHECK: sshll.2d [[EXT:v[0-9]+]], v0, #0
; CHECK: scvtf.2d v0, [[EXT]]
%res = sitofp <2 x i32> %in to <2 x double>
ret <2 x double> %res
}
define <2 x i32> @test_fptoui(<2 x float> %in) {
; CHECK-LABEL: test_fptoui:
; CHECK: fcvtzu.2s v0, v0
%res = fptoui <2 x float> %in to <2 x i32>
ret <2 x i32> %res
}
define <2 x i64> @test_fptosi(<2 x double> %in) {
; CHECK-LABEL: test_fptosi:
; CHECK: fcvtzs.2d v0, v0
%res = fptosi <2 x double> %in to <2 x i64>
ret <2 x i64> %res
}