llvm-6502/test/CodeGen/Mips/msa/vecs10.ll
Daniel Sanders 3c380d5e28 [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 12:14:50 +00:00

47 lines
1.3 KiB
LLVM

; Test the MSA intrinsics that are encoded with the VECS10 instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
define i32 @llvm_mips_bnz_v_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bnz_v_ARG1
%1 = tail call i32 @llvm.mips.bnz.v(<16 x i8> %0)
%2 = icmp eq i32 %1, 0
br i1 %2, label %true, label %false
true:
ret i32 2
false:
ret i32 3
}
declare i32 @llvm.mips.bnz.v(<16 x i8>) nounwind
; CHECK: llvm_mips_bnz_v_test:
; CHECK-DAG: ld.b [[R0:\$w[0-9]+]]
; CHECK-DAG: bnz.v [[R0]]
; CHECK: .size llvm_mips_bnz_v_test
@llvm_mips_bz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
define i32 @llvm_mips_bz_v_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bz_v_ARG1
%1 = tail call i32 @llvm.mips.bz.v(<16 x i8> %0)
%2 = icmp eq i32 %1, 0
br i1 %2, label %true, label %false
true:
ret i32 2
false:
ret i32 3
}
declare i32 @llvm.mips.bz.v(<16 x i8>) nounwind
; CHECK: llvm_mips_bz_v_test:
; CHECK-DAG: ld.b [[R0:\$w[0-9]+]]
; CHECK-DAG: bz.v [[R0]]
; CHECK: .size llvm_mips_bz_v_test
;