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307e97d066
The value of constant operands will be truncated to fit element width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212428 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.8 KiB
LLVM
46 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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; Check that building up a vector w/ only one non-zero lane initializes
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; intelligently.
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define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
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; CHECK-LABEL: one_lane:
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; CHECK: dup.16b v[[REG:[0-9]+]], wzr
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; CHECK-NEXT: ins.b v[[REG]][0], w1
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; v and q are aliases, and str is preferred against st.16b when possible
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; rdar://11246289
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; CHECK: str q[[REG]], [x0]
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; CHECK: ret
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%conv = trunc i32 %skip0 to i8
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%vset_lane = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv, i32 0
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%tmp = bitcast i32* %out_int to <4 x i32>*
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%tmp1 = bitcast <16 x i8> %vset_lane to <4 x i32>
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store <4 x i32> %tmp1, <4 x i32>* %tmp, align 16
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ret void
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}
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; Check that building a vector from floats doesn't insert an unnecessary
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; copy for lane zero.
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define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
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; CHECK-LABEL: foo:
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; CHECK-NOT: ins.s v0[0], v0[0]
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; CHECK: ins.s v0[1], v1[0]
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; CHECK: ins.s v0[2], v2[0]
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; CHECK: ins.s v0[3], v3[0]
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; CHECK: ret
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%1 = insertelement <4 x float> undef, float %a, i32 0
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%2 = insertelement <4 x float> %1, float %b, i32 1
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%3 = insertelement <4 x float> %2, float %c, i32 2
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%4 = insertelement <4 x float> %3, float %d, i32 3
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ret <4 x float> %4
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}
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define <8 x i16> @build_all_zero(<8 x i16> %a) #1 {
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; CHECK-LABEL: build_all_zero:
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; CHECK: movz w[[GREG:[0-9]+]], #0xae80
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; CHECK-NEXT: fmov s[[FREG:[0-9]+]], w[[GREG]]
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; CHECK-NEXT: mul.8h v0, v0, v[[FREG]]
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%b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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%c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
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ret <8 x i16> %c
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}
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