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a70f28ce7d
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for use on Xilinx FPGAs. For more information see: http://www.xilinx.com/tools/microblaze.htm http://en.wikipedia.org/wiki/MicroBlaze The current LLVM MicroBlaze backend generates assembly which can be compiled using the an appropriate binutils assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
1.7 KiB
LLVM
74 lines
1.7 KiB
LLVM
; Ensure that the select instruction is supported and is lowered to
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; some sort of branch instruction.
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;
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; RUN: llc < %s -march=mblaze -mattr=+mul,+fpu,+barrel | FileCheck %s
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declare i32 @printf(i8*, ...)
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@MSG = internal constant [13 x i8] c"Message: %d\0A\00"
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@BLKS = private constant [5 x i8*]
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[ i8* blockaddress(@brind, %L1),
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i8* blockaddress(@brind, %L2),
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i8* blockaddress(@brind, %L3),
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i8* blockaddress(@brind, %L4),
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i8* blockaddress(@brind, %L5) ]
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define i32 @brind(i32 %a, i32 %b)
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{
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; CHECK: brind:
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entry:
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br label %loop
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loop:
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%tmp.0 = phi i32 [ 0, %entry ], [ %tmp.8, %finish ]
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%dst.0 = getelementptr [5 x i8*]* @BLKS, i32 0, i32 %tmp.0
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%dst.1 = load i8** %dst.0
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indirectbr i8* %dst.1, [ label %L1,
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label %L2,
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label %L3,
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label %L4,
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label %L5 ]
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; CHECK: br {{r[0-9]*}}
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L1:
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%tmp.1 = add i32 %a, %b
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br label %finish
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; CHECK: br
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L2:
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%tmp.2 = sub i32 %a, %b
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br label %finish
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; CHECK: br
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L3:
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%tmp.3 = mul i32 %a, %b
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br label %finish
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; CHECK: br
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L4:
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%tmp.4 = sdiv i32 %a, %b
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br label %finish
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; CHECK: br
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L5:
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%tmp.5 = srem i32 %a, %b
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br label %finish
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; CHECK: br
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finish:
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%tmp.6 = phi i32 [ %tmp.1, %L1 ],
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[ %tmp.2, %L2 ],
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[ %tmp.3, %L3 ],
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[ %tmp.4, %L4 ],
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[ %tmp.5, %L5 ]
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call i32 (i8*,...)* @printf( i8* getelementptr([13 x i8]* @MSG,i32 0,i32 0),
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i32 %tmp.6)
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%tmp.7 = add i32 %tmp.0, 1
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%tmp.8 = urem i32 %tmp.7, 5
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br label %loop
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; CHECK: br
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}
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