Matt Arsenault d4786ed1de R600/SI: Match not instruction. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205837 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-09 07:16:16 +00:00

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InstPrinter

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MCTargetDesc

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TargetInfo

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AMDGPU.h

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AMDGPU.td

R600: Recommit 199842: Add work-around for the CF stack entry HW bug

2014-01-23 16:18:02 +00:00

AMDGPUAsmPrinter.cpp

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AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

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AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

R600: Take alignment into account when calculating the stack offset

2014-01-22 19:24:23 +00:00

AMDGPUFrameLowering.h

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AMDGPUInstrInfo.cpp

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AMDGPUInstrInfo.h

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AMDGPUInstrInfo.td

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

AMDGPUInstructions.td

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

AMDGPUIntrinsics.td

R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.

2014-03-31 18:21:18 +00:00

AMDGPUISelDAGToDAG.cpp

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

AMDGPUISelLowering.cpp

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

AMDGPUISelLowering.h

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

MachineInstr: introduce explicit_operands and implicit_operands ranges

2014-04-05 22:42:04 +00:00

AMDGPUMCInstLower.h

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AMDGPURegisterInfo.cpp

Make consistent use of MCPhysReg instead of uint16_t throughout the tree.

2014-04-04 05:16:06 +00:00

AMDGPURegisterInfo.h

Make consistent use of MCPhysReg instead of uint16_t throughout the tree.

2014-04-04 05:16:06 +00:00

AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

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AMDGPUSubtarget.h

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

AMDGPUTargetMachine.cpp

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AMDGPUTargetMachine.h

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AMDGPUTargetTransformInfo.cpp

Fix tabs

2014-04-04 20:13:08 +00:00

AMDILBase.td

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AMDILCFGStructurizer.cpp

R600: Don't viewCFG() under DEBUG() except on failure.

2014-03-24 20:29:02 +00:00

AMDILInstrInfo.td

R600: Enable -verify-machineinstrs in some tests.

2013-10-01 19:32:38 +00:00

AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

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AMDILIntrinsics.td

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AMDILISelLowering.cpp

R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp

2014-03-25 18:18:27 +00:00

AMDILRegisterInfo.td

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CaymanInstructions.td

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

CMakeLists.txt

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EvergreenInstructions.td

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

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R600ClauseMergePass.cpp

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R600ControlFlowFinalizer.cpp

R600: Correctly handle vertex fetch clauses the precede ENDIFs

2014-01-23 18:49:31 +00:00

R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600InstrFormats.td

R600: Use SchedModel enum for is{Trans,Vector}Only functions

2013-09-04 19:53:30 +00:00

R600InstrInfo.cpp

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R600InstrInfo.h

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R600Instructions.td

R600: Reorganize tablegen instruction definitions

2014-03-24 16:07:25 +00:00

R600Intrinsics.td

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R600ISelLowering.cpp

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

R600ISelLowering.h

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R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

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R600Packetizer.cpp

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R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

[Layering] Move InstVisitor.h into the IR library as it is pretty

2014-03-06 03:23:41 +00:00

R700Instructions.td

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SIAnnotateControlFlow.cpp

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SIDefines.h

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SIFixSGPRCopies.cpp

R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies

2014-04-07 19:45:45 +00:00

SIInsertWaits.cpp

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SIInstrFormats.td

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SIInstrInfo.cpp

R600/SI: Match not instruction.

2014-04-09 07:16:16 +00:00

SIInstrInfo.h

R600/SI: Implement shouldConvertConstantLoadToIntImm

2014-03-31 19:54:27 +00:00

SIInstrInfo.td

R600/SI: Lower 64-bit immediates using REG_SEQUENCE

2014-04-03 20:19:27 +00:00

SIInstructions.td

R600/SI: Match not instruction.

2014-04-09 07:16:16 +00:00

SIIntrinsics.td

R600/SI: Add intrinsic for BUFFER_LOAD_DWORD* instructions

2014-01-27 07:20:51 +00:00

SIISelLowering.cpp

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

2014-04-07 19:45:41 +00:00

SIISelLowering.h

Change shouldSplitVectorElementType to better match the description.

2014-03-31 20:54:58 +00:00

SILowerControlFlow.cpp

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SIMachineFunctionInfo.cpp

R600/SI: Implement spilling of SGPRs v5

2013-11-27 21:23:35 +00:00

SIMachineFunctionInfo.h

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SIRegisterInfo.cpp

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SIRegisterInfo.h

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SIRegisterInfo.td

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SISchedule.td

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SITypeRewriter.cpp

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