Bradley Smith 42c672649c [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205893 91177308-0d34-0410-b5e6-96231b3b80d8		2014-04-09 14:44:36 +00:00
..
advsimd.txt	[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.	2014-04-09 14:44:07 +00:00
arithmetic.txt	[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.	2014-04-09 14:42:11 +00:00
basic-a64-undefined.txt	[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.	2014-04-09 14:43:35 +00:00
bitfield.txt
branch.txt
canonical-form.txt	[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.	2014-04-09 14:44:22 +00:00
crc32.txt
crypto.txt
invalid-logical.txt
lit.local.cfg
logical.txt
memory.txt	[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.	2014-04-09 14:44:36 +00:00
scalar-fp.txt
system.txt	[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS.	2014-04-09 14:42:42 +00:00