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42d7ccfd8e
(shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) Replace it with: (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) This fixes test/CodeGen/ARM/smul.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33361 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
DAGCombiner.cpp | ||
LegalizeDAG.cpp | ||
Makefile | ||
ScheduleDAG.cpp | ||
ScheduleDAGList.cpp | ||
ScheduleDAGRRList.cpp | ||
ScheduleDAGSimple.cpp | ||
SelectionDAG.cpp | ||
SelectionDAGISel.cpp | ||
SelectionDAGPrinter.cpp | ||
TargetLowering.cpp |