mirror of
https://github.com/c64scene-ar/llvm-6502.git
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42de581b2f
anonymous regclass definition renaming. Change the generated code to emit register classes as properly namespace qualified entities like everything else. expose the actual class definition as an object, though this isn't quite usable yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22920 91177308-0d34-0410-b5e6-96231b3b80d8
271 lines
11 KiB
C++
271 lines
11 KiB
C++
//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of a target
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// register file for a code generator. It uses instances of the Register,
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// RegisterAliases, and RegisterClass classes to gather this information.
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//
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//===----------------------------------------------------------------------===//
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#include "RegisterInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "CodeGenRegisters.h"
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#include "Record.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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#include <set>
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using namespace llvm;
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// runEnums - Print out enum values for all of the registers.
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void RegisterInfoEmitter::runEnums(std::ostream &OS) {
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CodeGenTarget Target;
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
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EmitSourceFileHeader("Target Register Enum Values", OS);
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OS << "namespace llvm {\n\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << " enum {\n NoRegister,\n";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i)
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OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
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OS << " };\n";
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if (!Namespace.empty())
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OS << "}\n";
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OS << "} // End llvm namespace \n";
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}
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void RegisterInfoEmitter::runHeader(std::ostream &OS) {
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EmitSourceFileHeader("Register Information Header Fragment", OS);
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CodeGenTarget Target;
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const std::string &TargetName = Target.getName();
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std::string ClassName = TargetName + "GenRegisterInfo";
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OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n";
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OS << "namespace llvm {\n\n";
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OS << "struct " << ClassName << " : public MRegisterInfo {\n"
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<< " " << ClassName
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<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
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<< " const unsigned* getCalleeSaveRegs() const;\n"
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<< "};\n\n";
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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Target.getRegisterClasses();
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0].Namespace
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<< " { // Register classes\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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const std::string &Name = RegisterClasses[i].getName();
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OS << " extern TargetRegisterClass * const "<< Name <<"RegisterClass;\n";
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}
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OS << "} // end of namespace " << TargetName << "\n\n";
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}
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OS << "} // End llvm namespace \n";
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}
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// RegisterInfoEmitter::run - Main register file description emitter.
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//
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void RegisterInfoEmitter::run(std::ostream &OS) {
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CodeGenTarget Target;
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EmitSourceFileHeader("Register Information Source Fragment", OS);
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OS << "namespace llvm {\n\n";
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// Start out by emitting each of the register classes... to do this, we build
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// a set of registers which belong to a register class, this is to ensure that
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// each register is only in a single register class.
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//
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const std::vector<CodeGenRegisterClass> &RegisterClasses =
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Target.getRegisterClasses();
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std::set<Record*> RegistersFound;
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// Loop over all of the register classes... emitting each one.
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OS << "namespace { // Register classes...\n";
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// RegClassesBelongedTo - Keep track of which register classes each reg
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// belongs to.
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std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RegisterClasses[rc];
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// Give the register class a legal C name if it's anonymous.
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std::string Name = RC.TheDef->getName();
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// Emit the register list now.
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OS << " // " << Name << " Register Class...\n const unsigned " << Name
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<< "[] = {\n ";
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for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
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Record *Reg = RC.Elements[i];
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if (RegistersFound.count(Reg))
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throw "Register '" + Reg->getName() +
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"' included in multiple register classes!";
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RegistersFound.insert(Reg);
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OS << getQualifiedName(Reg) << ", ";
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// Keep track of which regclasses this register is in.
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RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
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}
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OS << "\n };\n\n";
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OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
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<< " " << Name << "Class() : TargetRegisterClass("
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<< RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << Name << ", "
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<< Name << " + " << RC.Elements.size() << ") {}\n"
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<< RC.MethodDefinitions << " };\n\n";
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}
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OS << "} // end anonymous namespace\n\n";
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// Now that all of the structs have been emitted, emit the instances.
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0].Namespace
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<< " { // Register class instances\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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OS << " " << RegisterClasses[i].getName() << "Class\t"
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<< RegisterClasses[i].getName() << "RegClassInstance;\n";
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OS << "}\n";
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}
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OS << "\nnamespace {\n";
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OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
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OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
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<< "RegClassInstance,\n";
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OS << " };\n";
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// Emit register class aliases...
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std::map<Record*, std::set<Record*> > RegisterAliases;
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const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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Record *R = Regs[i].TheDef;
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ListInit *LI = Regs[i].TheDef->getValueAsListInit("Aliases");
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// Add information that R aliases all of the elements in the list... and
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// that everything in the list aliases R.
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for (unsigned j = 0, e = LI->getSize(); j != e; ++j) {
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DefInit *Reg = dynamic_cast<DefInit*>(LI->getElement(j));
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if (!Reg) throw "ERROR: Alias list element is not a def!";
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if (RegisterAliases[R].count(Reg->getDef()))
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std::cerr << "Warning: register alias between " << getQualifiedName(R)
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<< " and " << getQualifiedName(Reg->getDef())
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<< " specified multiple times!\n";
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RegisterAliases[R].insert(Reg->getDef());
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if (RegisterAliases[Reg->getDef()].count(R))
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std::cerr << "Warning: register alias between " << getQualifiedName(R)
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<< " and " << getQualifiedName(Reg->getDef())
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<< " specified multiple times!\n";
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RegisterAliases[Reg->getDef()].insert(R);
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}
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}
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if (!RegisterAliases.empty())
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OS << "\n\n // Register Alias Sets...\n";
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// Emit the empty alias list
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OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
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// Loop over all of the registers which have aliases, emitting the alias list
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// to memory.
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for (std::map<Record*, std::set<Record*> >::iterator
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I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
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OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
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for (std::set<Record*>::iterator ASI = I->second.begin(),
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E = I->second.end(); ASI != E; ++ASI)
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OS << getQualifiedName(*ASI) << ", ";
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OS << "0 };\n";
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}
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OS << "\n const MRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
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OS << " { \"NOREG\",\t0,\t\t0,\t0 },\n";
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// Now that register alias sets have been emitted, emit the register
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// descriptors now.
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const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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const CodeGenRegister &Reg = Registers[i];
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OS << " { \"";
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if (!Reg.TheDef->getValueAsString("Name").empty())
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OS << Reg.TheDef->getValueAsString("Name");
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else
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OS << Reg.getName();
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OS << "\",\t";
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if (RegisterAliases.count(Reg.TheDef))
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OS << Reg.getName() << "_AliasSet,\t";
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else
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OS << "Empty_AliasSet,\t";
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// Figure out what the size and alignment of the spill slots are for this
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// reg. This may be explicitly declared in the register, or it may be
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// inferred from the register classes it is part of.
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std::multimap<Record*, const CodeGenRegisterClass*>::iterator I, E;
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tie(I, E) = RegClassesBelongedTo.equal_range(Reg.TheDef);
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unsigned SpillSize = Reg.DeclaredSpillSize;
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unsigned SpillAlign = Reg.DeclaredSpillAlignment;
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for (; I != E; ++I) { // For each reg class this belongs to.
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const CodeGenRegisterClass *RC = I->second;
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if (SpillSize == 0)
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SpillSize = RC->SpillSize;
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else if (SpillSize != RC->SpillSize)
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throw "Spill size for regclass '" + RC->getName() +
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"' doesn't match spill sized already inferred for register '" +
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Reg.getName() + "'!";
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if (SpillAlign == 0)
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SpillAlign = RC->SpillAlignment;
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else if (SpillAlign != RC->SpillAlignment)
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throw "Spill alignment for regclass '" + RC->getName() +
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"' doesn't match spill sized already inferred for register '" +
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Reg.getName() + "'!";
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}
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OS << SpillSize << ", " << SpillAlign << " },\n";
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}
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OS << " };\n"; // End of register descriptors...
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OS << "}\n\n"; // End of anonymous namespace...
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if (!RegisterClasses.empty()) {
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OS << "namespace " << RegisterClasses[0].Namespace
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<< " { // Register classes\n";
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for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
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OS << " TargetRegisterClass * const " << RegisterClasses[i].getName()
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<< "RegisterClass = &" << getQualifiedName(RegisterClasses[i].TheDef)
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<< "RegClassInstance;\n";
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}
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OS << "} // end of namespace " << RegisterClasses[0].Namespace << "\n\n";
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}
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std::string ClassName = Target.getName() + "GenRegisterInfo";
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// Emit the constructor of the class...
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OS << ClassName << "::" << ClassName
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<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
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<< " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
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<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
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<< " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
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// Emit the getCalleeSaveRegs method...
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OS << "const unsigned* " << ClassName << "::getCalleeSaveRegs() const {\n"
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<< " static const unsigned CalleeSaveRegs[] = {\n ";
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const std::vector<Record*> &CSR = Target.getCalleeSavedRegisters();
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for (unsigned i = 0, e = CSR.size(); i != e; ++i)
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OS << getQualifiedName(CSR[i]) << ", ";
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OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n";
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OS << "} // End llvm namespace \n";
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}
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