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https://github.com/c64scene-ar/llvm-6502.git
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c3cee57f7d
We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
124 lines
4.2 KiB
C++
124 lines
4.2 KiB
C++
//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides X86 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86MCTARGETDESC_H
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#define X86MCTARGETDESC_H
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#include "llvm/Support/DataTypes.h"
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#include <string>
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCRelocationInfo;
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class Target;
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class StringRef;
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class raw_ostream;
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extern Target TheX86_32Target, TheX86_64Target;
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/// DWARFFlavour - Flavour of dwarf regnumbers
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///
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namespace DWARFFlavour {
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enum {
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X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
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};
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}
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/// N86 namespace - Native X86 register numbers
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///
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namespace N86 {
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enum {
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EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
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};
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}
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namespace X86_MC {
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std::string ParseX86Triple(StringRef TT);
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in
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/// the specified arguments. If we can't run cpuid on the host, return true.
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bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
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/// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
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/// the 4 values in the specified arguments. If we can't run cpuid on the
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/// host, return true.
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bool GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
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unsigned *rEBX, unsigned *rECX, unsigned *rEDX);
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void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model);
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unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
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void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
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/// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
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/// This is exposed so Asm parser, etc. do not need to go through
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/// TargetRegistry.
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MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS);
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}
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MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx);
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MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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/// createX86MachObjectWriter - Construct an X86 Mach-O object writer.
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MCObjectWriter *createX86MachObjectWriter(raw_ostream &OS,
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bool Is64Bit,
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uint32_t CPUType,
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uint32_t CPUSubtype);
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/// createX86ELFObjectWriter - Construct an X86 ELF object writer.
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MCObjectWriter *createX86ELFObjectWriter(raw_ostream &OS,
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bool IsELF64,
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uint8_t OSABI,
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uint16_t EMachine);
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/// createX86WinCOFFObjectWriter - Construct an X86 Win COFF object writer.
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MCObjectWriter *createX86WinCOFFObjectWriter(raw_ostream &OS, bool Is64Bit);
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/// createX86_64MachORelocationInfo - Construct X86-64 Mach-O relocation info.
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MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx);
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/// createX86_64ELFORelocationInfo - Construct X86-64 ELF relocation info.
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MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx);
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} // End llvm namespace
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// Defines symbolic names for X86 registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "X86GenRegisterInfo.inc"
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// Defines symbolic names for the X86 instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "X86GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "X86GenSubtargetInfo.inc"
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#endif
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