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https://github.com/c64scene-ar/llvm-6502.git
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register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
180 lines
5.8 KiB
C++
180 lines
5.8 KiB
C++
//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARMMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-emitter"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMInstrInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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class ARMMCCodeEmitter : public MCCodeEmitter {
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ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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MCContext &Ctx;
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public:
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ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
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: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
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}
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~ARMMCCodeEmitter() {}
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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unsigned getBinaryCodeForInstr(const MCInst &MI) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
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unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
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return getMachineOpValue(MI, MI.getOperand(OpIdx));
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}
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unsigned getNumFixupKinds() const {
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assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
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return 0;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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static MCFixupKindInfo rtn;
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assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
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return rtn;
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}
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static unsigned GetARMRegNum(const MCOperand &MO) {
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// FIXME: getARMRegisterNumbering() is sufficient?
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assert(0 && "ARMMCCodeEmitter::GetARMRegNum() not yet implemented.");
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return 0;
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}
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void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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OS << (char)C;
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++CurByte;
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}
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void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
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raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, CurByte, OS);
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Val >>= 8;
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}
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}
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void EmitImmediate(const MCOperand &Disp,
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unsigned ImmSize, MCFixupKind FixupKind,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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int ImmOffset = 0) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
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TargetMachine &TM,
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MCContext &Ctx) {
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return new ARMMCCodeEmitter(TM, Ctx);
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}
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void ARMMCCodeEmitter::
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EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
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assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented.");
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO) const {
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if (MO.isReg())
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// FIXME: Should shifted register stuff be handled as part of this? Maybe.
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return getARMRegisterNumbering(MO.getReg());
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else if (MO.isImm())
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// FIXME: This is insufficient. Shifted immediates and all that... (blech).
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return static_cast<unsigned>(MO.getImm());
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else {
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#ifndef NDEBUG
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errs() << MO;
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#endif
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llvm_unreachable(0);
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}
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return 0;
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}
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void ARMMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = TII.get(Opcode);
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uint64_t TSFlags = Desc.TSFlags;
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// Keep track of the current byte being emitted.
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unsigned CurByte = 0;
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// Pseudo instructions don't get encoded.
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if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
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return;
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++MCNumEmitted; // Keep track of the # of mi's emitted
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// FIXME: TableGen doesn't deal well with operands that expand to multiple
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// machine instruction operands, so for now we'll fix those up here.
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switch (Opcode) {
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case ARM::ADDrs:
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case ARM::ANDrs:
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case ARM::BICrs:
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case ARM::EORrs:
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case ARM::ORRrs:
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case ARM::SUBrs: {
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// The so_reg operand needs the shift ammount encoded.
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unsigned Value = getBinaryCodeForInstr(MI);
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unsigned ShVal = MI.getOperand(4).getImm();
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unsigned ShType = ARM_AM::getShiftOpcEncoding(ARM_AM::getSORegShOp(ShVal));
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unsigned ShAmt = ARM_AM::getSORegOffset(ShVal);
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Value |= ShType << ARMII::ShiftTypeShift;
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Value |= ShAmt << ARMII::ShiftShift;
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EmitConstant(Value, 4, CurByte, OS);
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break;
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}
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default: {
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unsigned Value = getBinaryCodeForInstr(MI);
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EmitConstant(Value, 4, CurByte, OS);
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break;
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}
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}
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}
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// FIXME: These #defines shouldn't be necessary. Instead, tblgen should
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// be able to generate code emitter helpers for either variant, like it
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// does for the AsmWriter.
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#define ARMCodeEmitter ARMMCCodeEmitter
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#define MachineInstr MCInst
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#include "ARMGenCodeEmitter.inc"
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#undef ARMCodeEmitter
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#undef MachineInstr
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