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42fac8ee3b
register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.1 KiB
LLVM
39 lines
1.1 KiB
LLVM
;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
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;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
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; should run on .s source files rather than using llc to generate the
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; assembly.
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define i32 @foo(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: foo
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; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
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; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
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tail call void @llvm.trap()
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ret i32 undef
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}
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define i32 @f2(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK: f2
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; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
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; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
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%add = add nsw i32 %b, %a
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ret i32 %add
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}
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define i32 @f3(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK: f3
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; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
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; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
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%mul = shl i32 %b, 3
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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declare void @llvm.trap() nounwind
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